JPS6237412B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data processing system in which a plurality of homogeneous processing devices, such as a channel device, require that a microprogram be loaded into a control storage device at system start-up. In contrast, the present invention relates to a microprogram loading control method for reducing loading processing time by loading microprograms simultaneously.

[Technology background]

Modern large data processing systems have many multiplexer channels, such as 16 or 32.
It is common to have MXC or block multiplexer channel BMC. These channel devices must have a control microprogram loaded into their own control memory device (RMA) during initialization to start up the system.

Conventionally, when starting up a system, the service processor SVP would sequentially load microprograms to each processing device that required microprogram loading, such as the channel devices mentioned above, one by one. The loading time was extremely long.

[Object and structure of the invention]

An object of the present invention is to shorten the loading time by simultaneously loading microprograms to multiple processing devices. , for each group, the SVP executes the loading process at the same time.

The arrangement of the present invention thereby comprises a plurality of processing units, each having a control memory that requires loading of a microprogram, and a mode register that controls loading of the microprogram; In a data processing system in which microprograms are loaded into the control storage devices of multiple processing units under the control of a service processor, a common data bus and a common timing signal are connected from the service processor to all of the processing units. and the means to
means for setting a mode in the mode register of each processing unit from the service processor; means for writing data to sequential addresses in the control memory; means for reading data from sequential addresses in the control memory; and detecting errors in the data. and means for notifying the service processor of the detected data error, and the service processor sets a mode in the mode register of the same type of processing device for each type of processing device in the system, and The present invention is characterized in that the same microprogram is simultaneously loaded into processing devices of the same type using the common data bus and timing signal.

[Embodiments of the invention]

The present invention will be explained below using examples.

FIG. 1 is a configuration diagram of a system according to an embodiment of the present invention. In this diagram, 1 is the service processor SVP
where 2-0, 2-i, and 2-n represent _{CH 0 ,} CHi, and CHn among the n+1 channel devices CH 0 to CHn. 3 is a control storage device CS, 4 is an address register CSA for CS, 5 is a mode register,
6 is a decoder, 7 is a comparator, 8 is a timing signal line, 9 is a data bus, 10-0, 10-i, 10
-n indicates a mode setting signal line for CH ₀ , CHi, and CHn, respectively, and 11 indicates a check result signal line.

Among channel devices CH ₀ to CHn, CH ₀ to
CHi Block Multiplexer Channel BMC
and the others are a multiplexer channel and a selector channel. In this example, CH ₀
An example will be explained in which CHi to CHi are loaded at the same time as processing devices of the same type using the same microprogram. Although not shown in the figure, the components 3 to 7 shown in CH ₀ are of course similarly provided in other CH ₁ to CHn.

The CS 3 stores specific control microprograms for each type of channel device.

The CSA4 indicates the address of the CS3 and has an increment mechanism that increments the address by 1 every time it is accessed.

Mode register 5 holds a mode code. The mode code is set by SVP and CS3
A write mode in which data is written to CS3, a tick mode in which data written in CS3 is read and ticked, and a non-operation state in which no operation is performed are specified.

The decoder 6 decodes the mode code set in the mode register 5 and generates an operation control signal for the set write mode or check mode according to the timing signal.

In check mode, comparator 7
The data of each address sequentially read from
Compare with the original data correspondingly supplied from SVP,
Notify the results to SVP.

Timing signal line 8 connects all channel devices CH ₀ that require microprogram loading.
Commonly connected to CHn to CHn. It is used to drive the decoder 6.

Like the timing signal line 8, the data bus 9 is also commonly connected to all channel devices _CH0 to CHn, and is used to transfer microprograms from SVP to CS3.
and is used to supply the mode code to the mode register 5.

The mode setting signal lines 10-0 to 10-n are
A separate provision is made from the SVP to each channel device to select the mode register in which the SVP should set the mode code.

The check result signal line 11 wires the check result output signal of the comparator 7 in each channel device.
Combine with OR and transfer to SVP. Therefore, in the check mode, when at least one of the output signals of the respective comparators ₇ of the block multiplexer channels CH0 to CHi of the same type indicates an error condition (for example, a "1" level signal),
The signal line 11 becomes "1" level. This results in
The SVP can recognize that the data at the address currently being checked in the CS3 data of any channel device is in error.

FIG. 2 shows the operational flow of the embodiment system shown in FIG. The operation of the embodiment will be described below with reference to both figures.

SVP is the mode setting signal line 10-0 to 10
-i is sequentially activated, the write mode code is output onto the data bus 9, and each CH ₀ to
Set the write mode code in mode register 5 of CHi. Still other channel devices are in a non-operational state.

SVP outputs a timing signal to timing signal line 8, and further outputs a timing signal to data bus 9 of CS3.
Outputs the microprogram data to be stored at the address specified by the CSA 4, that is, at address 0 initially. The decoder 6 of each CH ₀ to CHi is
Set CSA4 to address 0 and store the data on data bus 9 to address 0 of CS3.

Set the address of CSA4 to +1.

SVP checks whether the transfer of all program data to be loaded has been completed, and if there is any remaining program data, returns. When loading is completed, the process moves to the next check mode.

In the same manner as above, set the check mode code in the mode register of each CH ₀ to CHi.

SVP outputs a timing signal to timing signal line 8 and further outputs data corresponding to the address indicated by CSA 4 to data bus 9. each
CH ₀ to CHi seriously reset CSA4 to address 0 and read data from address 0 of CS3.

Increments the contents of address register CSA by +1.

Comparator 7 is used to write the data read from the address indicated by CS4 of CS3, which is currently the first address 0, and the original data for comparison that SVP outputs again to data bus 9. The result is output to the tick result signal line 11.

The SVP recognizes whether the data at the address specified by the CSA 4 is error data.

If the data is normal, check whether all data has been checked. If not completed, return to step 3 and check the data at the next address of CS. On the other hand, if all data has been checked, the loading process ends normally.

If a data error is recognized in the SVP, the SVP performs the specified error handling.

As described above, similar processing devices CH ₀ to CHi
When the loading for is finished, the SVP
Similar processing is performed on the next group of processing devices of the same type, and loading for all processing devices is completed in the same manner.

〔Effect of the invention〕

According to the present invention, a large number of processing devices are grouped into the same type of devices, and loading is executed simultaneously for each group, so that the processing time can be significantly reduced compared to the conventional method.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a flow diagram showing an example of its operation. In the figure, 1 is a service processor SVP, 2-0 to 2-n are channel devices, and 3 is a control storage device.
CS, 4 is address register CSA, 5 is mode register, 6 is decoder, 7 is comparator, 8 is timing signal line, 9 is data bus, 10-0 to 10
-n represents a mode setting signal line, and 11 represents a check result signal line.

Claims (1)

[Claims] 1. It has a plurality of processing units, each equipped with a control storage device that requires microprogram loading, and a mode register that controls microprogram loading, and when the system is initialized, under the control of a service processor, In a data processing system in which a microprogram is loaded into a control storage device of a plurality of processing units, means for connecting a common data bus and a common timing signal from a service processor to all of the processing units; means for setting a mode in a mode register of each processing unit; means for writing data to sequential addresses of the control storage; means for reading data from sequential addresses of the control storage; and means for detecting errors in the data; The service processor is equipped with a means for notifying the service processor of errors in the data that has been processed, and the service processor
Microprogram loading control characterized by setting a mode in mode registers of processing devices of the same type, and simultaneously loading the same microprogram to the processing devices of the same type using the common data bus and timing signal. method.