JPS6237721A - Timing signal generating circuit - Google Patents

Abstract

PURPOSE:To produce such a timing signal that can avoid the competition of plural circuits that give the asynchronous accesses to a single circuit by a common bus, by controlling a partial timing generating circuit sharing a counter with the external decoding output. CONSTITUTION:When an external input 12 is set at H, and RS type FF is set. Then, the output of a register 20 is inverted to H in response to an upper bit of a counter 60 given immediately after said FF is set. Then, an H signal is impressed to a partial timing generating circuit 40 sharing a counter 60 from a decoder 30. Thus, the circuit 40 produces the partial timing signal in response to the output change of the counter 60 and delivers it to a command bus via a register 50. At the same time, the FF is reset by the output of the partial timing signal and the timing signal produced by the circuit 40 is prevented. Thus, it is possible to produced the timing signal with which the competition can be prevented among plural circuits that give the asynchronous accesses to a single circuit via a common bus through the external control of the circuit 40 without using any complicated constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a timing signal generation circuit for system equipment composed of electronic circuits.

Background of the Invention In recent years, conductor technology (tFi) has progressed, and large-scale electronic circuit systems have become known as large-scale integrated circuits (LSI).
It now fits inside one electronic component. However, LSI
If the system to be inserted into the device is unnecessarily large, the area of the LSI chip will be too large, which will reduce the number of chips that can be made and reduce the yield of chips and knobs. Therefore, it is desirable for the system that supports LSI to be as small as possible! It is desirable to downsize the timing signal generation circuit, which can be made considerably smaller with careful thought.
be caught.

An example of the above-mentioned conventional timing signal generation circuit will be described below while referring to the drawings.

FIG. 7 shows a block diagram of a conventional timing signal generation circuit. In FIG. 7, 1 is a counter, 2 is a read-only memory (ROM), 3 is a register, MCK is a mask clock, and the clock input signal terminal of counter 1 is connected to the clock input signal terminal of register 3. The master clock MCK is input, the output signal terminal of the counter 1 is connected to the address input signal terminal of the ROM2, the data output signal terminal of the ROM2 is connected to the input signal terminal of the register 30, and the ROM2 has an att. The timing is written as 1, assuming that the time per address is the cycle of the master clock MGK.

The operation of the timing generator circuit configured as shown below will be explained below.

First, master clock MCK is input to the clock input signal terminal of counter 1, and counter 1 is sequentially incremented by the rising edge of MCK. Since the timing is written in ROM2 using the address as time,
Timing is generated on the data output signal terminal of ROM2 by an increase in the output signal value of counter 1, that is, an increase in the address input signal value of ROM2. However, the timing signal often contains a hazard due to the delay of the counter 1 and the ROM 2, and when the timing signal is manually input to the register 3, a timing signal free of hazards is generated on the output signal terminal of the register 3.

Problems to be Solved by the Invention However, in the above configuration, one circuit (two circuits) and a plurality of circuits (Aφ open circuit A1 circuit, A2 circuit, ......, An circuit (n : positive integer)) are connected by a common bus, Aφ open circuit A1 circuit, ..., An circuit is converted into two circuits using the common bus, mutually asynchronously, In the case of a system that accesses data, it is extremely difficult to design a timing signal generation circuit, and even if it were possible to design it, there would be problems such as the configuration becoming complicated and the scale of the hardware increasing. Was.

The present invention overcomes the above problems and has one circuit (two circuits) and a plurality of circuits (Aφ open circuit A1 circuit).

. . ., An circuit) are connected by a common bus, and the Aφ open circuit A1 circuit, . , and provides a timing signal generation circuit that allows easy configuration of a system so as to access data to two circuits.

Means for Solving the Problems The timing signal generation circuit of the present invention controls a partial timing generation circuit that generates timing signals necessary for accessing a target circuit using an external signal through a decoder, and In order to solve the above problem, it is necessary to use circuit A (i = 0.1, 2... +
n) has a part 't timing generation circuit which generates all the timing signals accessing the two circuits, and it suffices if there are (n+1) timing signal generation circuits of the present invention having a common counter, and each partial timing generation circuit is The Aφ circuit, A1 circuit, . . . , An circuit are controlled by external signals through each decoder so that they do not access two circuits at the same time.

Operation The present invention has the above-described configuration, so that the counting circuit can simultaneously perform one counting circuit.
This makes it easier to generate timing signals.

Embodiment A timing signal generation circuit according to an embodiment of the present invention will be explained below with reference to the drawings).6 Fig. 1 is a complete block diagram of a timing signal generation circuit according to a first embodiment of the present invention. In FIG. 1, 1o has two input signal terminals 11 and 12 and one output signal terminal 13, and is set by the high level of the input signal terminal 12 and the high level of the input signal +4 terminal 11. 20 is a set-reset flip-flop that is reset by 1'-), and has a clock input signal terminal 21 of 1'-), one input signal terminal 22, and one output signal terminal 23. This is a register that holds all the input signals by the edge and outputs them to the output signal terminal 23. 30 has two input signal terminals 31 and 32 and one output signal terminal 33, and when the input signal terminal 31 is at a high level, the input signal is This is a decoder whose output signal is at a high level only when all bits of the terminal 32 are at a low level, and 40 is a decoder that outputs a high level signal from two input signal terminals 41.
42 and one output signal terminal 43, when the input signal terminal 42 is at a high level, the 1' out-of-off signal is determined according to the input signal value, and when the input signal terminal 42 is at a low level, the output signal is determined. This is a partial timing generation circuit in which all bits of the signal on the terminal 43 are at a low level.
It is a register which has four output signal terminals 53, holds the input signal according to the rising edge of the clock input signal, and outputs it to the output signal terminal 53. This is a counter that counts the falling edges of the clock input signal and outputs the count value to the output signal terminal 62, and is connected to the terminal for 1 bit among the output signal terminals 63 of the register 50 and the input signal terminal of the set/reset flip-flop 1°. 11 is connected, the output signal terminal 13 of the seven-point reset flyknob flop 10 is connected to the input signal terminal 22 of the register 2o), the output signal terminal 23 of the register 20 is connected to the input signal terminal 31 of the decoder 30, and the input signal terminal 31 of the decoder 30 is connected. output signal terminal 3
3 is connected to the input signal terminal 42 of the partial timing generation circuit 4o, the output signal terminal 43 of the partial timing generation circuit 40 is connected to the input signal terminal 52 of the register 50, and the most significant bit of the output signal terminal 62 of the counter 60 is connected. The input signal terminal 21 of the register 20 is connected to the terminal corresponding to the input signal terminal 21 of the register 20, and the input signal terminal 41 of the partial timing generation circuit 40 is connected to the terminal corresponding to at least one bit of the output signal terminal 62 of the counter 6o. The input signal terminal 61 of 60 and the input signal terminal 51 of the register 50 are connected.

The operation of the timing signal generation circuit configured as described above will be explained below with reference to FIG.

Input signal terminal 1 of set-reset flip-flop 1o
2 is set to a high level even temporarily, the set-reset flip-flop 10 is set, and the input signal terminal 22 of the register 20 is set to a high level. The most significant bit of the output signal of counter 2o immediately after that, that is, register 2
The rising edge of the 0 clock input signal causes the input signal terminal 31 of the decoder 30 to go high. At that time, if the input signal terminals 32 of the f-gouda 30 are all at low level, the output signal terminal 33 of the decoder 3o, that is, the input signal terminal 42 of the partial timing generation circuit 40 becomes high level, and the output signal of the partial timing generation circuit 40 On the terminal 43, depending on the change in the output signal of the counter 6Q,
A timing signal is generated on the output signal terminal 43 of the partial timing generation circuit 40. The early timing signal has a gate or a large delay, so it is synchronized with the clock input signal of the counter 6o, and the timing signal without a gate and with a small delay is output from the output signal terminal 63. Output.

One bit of the timing signal is input to the input signal terminal 11 of the set-reset flip-flop 10, and resets the set-reset flip-flop 10i. When the set-reset flip-flop 10 is reset or when the terminal for at least one bit of the input signal terminal 32 of the decoder 30 is at level 7, the input signal terminal 42 of the partial timing generation circuit 40
becomes low level, and all output signals of partial timing generation circuit 4Q become low level. Therefore register 50
All output signals become low level.

As described above, according to this embodiment, by replacing the timing signal generation circuit with an externally controllable timing signal generation circuit, which can also be called a partial timing generation circuit, a predetermined timing signal is generated only when necessary. can occur.

A second embodiment of the present invention will be described below with reference to the drawings.

2, 3, 4, and 5 are block diagrams of a timing signal generation circuit showing a second embodiment of the present invention,
All of the above four drawings collectively show one timing signal generation circuit. FIG. 6 is a timing chart of a timing signal generation circuit according to a second embodiment of the present invention. Figures 2, 3, and 4.

As shown in FIG. 5, the timing signal generation circuit according to the second embodiment of the present invention uses a common counter, which is a component of the first embodiment, and has the same configuration as the first embodiment. It consists of two timing signal generation circuits. FIG. 2 shows the entire common counter, and FIGS. 3, 4, and 5 each show one of the three signal generating circuits excluding only the counter. The difference in the configuration of the second embodiment from that of the first embodiment is that the set-reset flip-flop 1100°210 corresponds to the center-reset flip 70 knob 10.
0.3100 is configured with two NOR gates as shown in the figure, and decoder 1 corresponding to decoder 3o
300, 2300, and 3300 are each constructed from the combinational circuits shown in the figure, and the partial timing generation circuit 4
Partial timing generation circuit 1400, 240 corresponding to 0
0.3400 is configured with an inverter and two AND gates as shown in the figure, respectively, and the counter shown in FIG. 6
The register 1200 corresponds to the register 1200 that the counter 60 in FIG.
The output signal terminal 123o of the decoder 2300, the input signal terminal 2320 of the decoder 2300, and the output signal terminal 332 of the decoder 33000A
1 is connected, which means that the output signal terminal 2230 of the register 220'O and the input signal terminal 3322 of the decoder 330o are connected.

Note that the clock input signal terminal 2 of the counter 2
In FIG. 61, a clock shown as MGK in FIG. 6 is input.

Regarding the timing signal generation circuit configured as described above, the timing signal generation section shown in FIG. 3 is part A, the timing signal generation part shown in FIG. 4 is part B, and the entire timing signal generation part 9C shown in FIG. The operation will be explained below.

As shown in the timing chart in Figure 6, A
Assume that the timing signals shown in FIG. 7 are requested for the AIT, BIT, and CIT periods for the AIT, BIT, and CIT sections, respectively.

At time T1, the B section and the 0 section accept the request, and the B section generates the timing shown in FIG. 8 at time T1, but the CB receives the timing shown in FIG. have to wait for it to occur. Time T.

At time T4, Part A accepts the request.
, the timing shown in Figure 8 is generated, and part 0 is also A.
The output signal of the register 12QO of the section waits for the timing shown in FIG. 8 to be generated. Part 0 generates the timing shown in FIG. 8 for the first time at time T5.

As mentioned above, all the components of the timing generation circuit are the A part, B part, and 0 part, and the A part, B part, and 0 part are prioritized, and the one with the higher priority is the timing of the one with the lower priority. By fully controlling generation, it is easy to generate timing signals for a system in which one circuit and a plurality of circuits are connected via a common bus, and the plurality of circuits are accessed by the one circuit K. It is something that becomes.

Note that in the first embodiment and the second embodiment, the sector reset flip-flop 10.1100 used as a component
, 2100 and 3100 may be combinational circuits instead of set/reset flip-flops.

Effects of the Invention As described above, the present invention has the advantage that the timing signal generated by the partial timing generation circuit can be controlled.
This facilitates timing generation in a system in which a plurality of circuits transfer data to each other using a common bus tone.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a timing signal generation circuit in the first embodiment of the present invention, FIGS. 2, 3, 4, and 5.
The figure is a block diagram of the timing signal generation circuit in the second embodiment, FIG. 6 is a timing chart diagram of the timing signal generation circuit in the second embodiment, and FIG. 7 is a diagram of the conventional timing signal generation circuit. It is a block diagram. FIG. 8 is a timing chart of timing signals for controlling the external circuit. 10... Cenotricenotophrinopfuronop, 2o
...Register, 30...Decoder, 40.
...Mountain portion timing generation circuit, 50...Register, 60...Counter, 11. 12, 22
, 31. 332.41.42, 52.61... Input signal terminal, 21.61.61... Clock input signal terminal, 13.23, 33, 43, 53.62...
・Output signal terminal, 63...Counter, 64...
...Inverter, MCK...Master clock, MCK2...Test point, AI, BI
, CI...timing request signal, AOl,
AO2, AO3, BOl, BO2゜BO3, COl
, CO2, CO3--1 imitation signal, 1...
Counter, 2... Read only memory IJ (RO
M), 3...Register, A, 9...Input signal terminal, 6...Output signal terminal, 7...
...Address input signal terminal, 8...Data output signal terminal, 4゜5...Clock input signal terminal,
1100.2100. 2200...Set/reset flip-flop, 1200.2200.3200=----register,
1300.2300.3300...decoder,
1400.2400.3400...Partial timing generation circuit, 1500.2500.3500-...
-Register, 1101.2101.3101. 110
2゜2102.3102...2 Kaa Gate, 2301. 1401.2401.3401.1402.2402゜3402...2 person Kaand gate, 3301.
...Three people Kaand Gate, 2302.3302.
3303. 1403.2403.3403 --- Inverter, C
N1゜C1N2, CN3, CN4...
Terminals showing connections between Figures 2, 3, 4, and 5, 1210° 2210.3210, 1510, 251
0.3510...Clock input signal terminal, 11
10,2110°3110.1120,2120,31
20,1220°2220.3220,1310,23
10,3310°2320.3321. 3322.1
410.2410°3410.1420,2420,3
420,1621. 2521. 3521. 1522, 2522, 352
2゜1523.2523.3523... Input signal terminal, 1130.2130, 3130, 1230, 2
230°3230.1330,2330,3330,1
431. 2431. 3431. 1432.2432.343
2. 1433.2433,3433,1531. 2531
. 3531. 1532, 2532, 3532, 1533
゜2633.3633・・・Output signal terminal. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2/'7C, K CK2 Figure 3 Figure 5 Figure 6 C1-C O3 Knee = T

Claims (2)

[Claims] (1) A counter C that has a clock input signal terminal and an output signal terminal, counts the edges of the clock input signal, and outputs the counted value on the output signal terminal, and has an input signal terminal and an output signal terminal, It has a set/reset flip-flop L whose held data changes depending on the level of the input signal, a clock input signal terminal, an input signal terminal, and an output signal terminal, and which holds the input signal according to the edge of the clock input signal and has an output signal terminal. a decoder D which has an input signal terminal and an output signal terminal, and whose output signal is at a predetermined level only when the input signal is predetermined data; and a decoder D, which has an input signal terminal and an output signal terminal. ,
The output signal is determined according to the data on the second input signal terminal only when the first input signal terminal is at a predetermined level, and when the first input signal terminal is different from the level of the first input signal terminal. a partial timing generator T whose output signal is set to predetermined data; a clock input signal terminal; The input signal terminal of counter C and the input signal terminal of register R2 are connected, and the terminal for the most significant bit among the output signal terminals of counter C and the clock input signal terminal of register R1 are connected. connected,
One of the output signal terminals of the counter C is connected to a second input signal terminal of the partial timing generator T, and a first input signal terminal of the set-reset flip-flop L and one output signal terminal of the register R2 are connected. is connected, the output signal terminal of the set-reset flip-flop L is connected to the input signal terminal of the register R1, one input signal terminal of the decoder D is connected to the output signal terminal of the register R1,
Timing characterized in that the first input signal terminal of the partial timing generator T and the output signal terminal of the decoder D are connected, and the input signal terminal of the register R2 and the output signal terminal of the partial timing generator T are connected. Signal generation circuit. (2) The timing signal generation circuit according to claim 1, wherein the set-reset flip-flop L is replaced with a combinational circuit.