JPS6242536Y2 - - Google Patents

Info

Publication number
JPS6242536Y2
JPS6242536Y2 JP1981115225U JP11522581U JPS6242536Y2 JP S6242536 Y2 JPS6242536 Y2 JP S6242536Y2 JP 1981115225 U JP1981115225 U JP 1981115225U JP 11522581 U JP11522581 U JP 11522581U JP S6242536 Y2 JPS6242536 Y2 JP S6242536Y2
Authority
JP
Japan
Prior art keywords
bonding
pad
aluminum
sagging
thick film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1981115225U
Other languages
Japanese (ja)
Other versions
JPS5820538U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1981115225U priority Critical patent/JPS5820538U/en
Publication of JPS5820538U publication Critical patent/JPS5820538U/en
Application granted granted Critical
Publication of JPS6242536Y2 publication Critical patent/JPS6242536Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07141—Means for applying energy, e.g. ovens or lasers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5434—Dispositions of bond wires the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Description

【考案の詳細な説明】 本考案は混成集積回路中のワイヤボンドのボン
デイング用アルミパツドの形状を改良し、ワイヤ
ボンドの信頼性を向上させたものたものである。[Detailed Description of the Invention] The present invention improves the reliability of wire bonds by improving the shape of aluminum pads for bonding wire bonds in hybrid integrated circuits.

従来、混成集積回路装置の製造にあたつて、一
般にアルミパツド３は図示しない素材板から打抜
き等により「ダレ」つまり傾斜部分を有してお
り、第３図に示すようにそのダレ面３ａを厚膜基
板側に表面処理して例えば半田付等によつて固着
していた。しかし、同図ｂに示すようにボンデイ
ング面の傾きが生じやすく、第４図ａ〜ｃに示す
ようなボンデイング装置のウエツジ８との関係の
不具合が生じ、ボンデイング強度の劣化の要因と
なつていた。 Conventionally, when manufacturing a hybrid integrated circuit device, the aluminum pad 3 is generally punched out of a material plate (not shown) to have a "sagging" or sloping part, and the sagging surface 3a is made thicker as shown in FIG. The membrane substrate was surface-treated and fixed by, for example, soldering. However, as shown in Figure 4(b), the bonding surface tends to tilt, causing problems in the relationship with the wedge 8 of the bonding device as shown in Figures 4(a) to 4(c), which is a factor in deterioration of bonding strength. .

本考案は上記欠点を解消できる混成集積回路装
置を提供することを目的とする。 SUMMARY OF THE INVENTION An object of the present invention is to provide a hybrid integrated circuit device that can overcome the above-mentioned drawbacks.

ここで、従来のようにダレ面３ａを厚膜基板側
にして固着した場合、第３図ｂに示すようにボン
デイング面に傾きが生じる原因を解析した結果、
その主な原因は第５図ａに示すように、半田７の
表面張力は半田７とアルミパツド３とのぬれ界面
において、図中矢印で示すようにダレ面３ａの接
線方向に作用しており、そして、打抜き等により
発生するダレ面３ａの形状のばらつきによつて、
ぬれ界面の部分ごとに表面張力の大きさが異な
り、その為、全体のバランスが崩れる事によつ
て、前述したような傾きが生じている事を見出し
た。 Here, as a result of analyzing the cause of the tilting of the bonding surface as shown in FIG. 3b, when bonding is done with the sagging surface 3a facing the thick film substrate as in the conventional case,
The main reason for this is that, as shown in Figure 5a, the surface tension of the solder 7 acts in the tangential direction of the sagging surface 3a at the wet interface between the solder 7 and the aluminum pad 3, as shown by the arrow in the figure. Due to variations in the shape of the sagging surface 3a caused by punching etc.,
It was discovered that the magnitude of surface tension differs for each part of the wetting interface, and as a result, the overall balance is disrupted, resulting in the above-mentioned inclination.

そして、本考案はそのような事実に鑑みなされ
たものであつて、第２図に示すように、その形状
のばらつきの小さい非ダレ面３ｂを厚膜基板側に
して固着する事により、アルミパツド３の上面と
厚膜基板表面，半導体チツプ表面等の平行度を確
保しようとするものであり、本考案のようにして
固着する場合、第５図ｂに示すように、半田７の
表面張力は、半田７とアルミパツド３とのぬれ界
面の全周で均等に図中矢印で示すように下方に作
用する事になり、ボンデイング面の基板に対する
傾き、及びその傾きのばらつきを低減できる。 The present invention has been developed in view of this fact, and as shown in FIG. The purpose is to ensure parallelism between the upper surface, the thick film substrate surface, the semiconductor chip surface, etc., and when bonding as in the present invention, the surface tension of the solder 7 is as shown in FIG. 5b. The wetting interface between the solder 7 and the aluminum pad 3 is uniformly acted downward as shown by the arrow in the figure over the entire circumference, and the inclination of the bonding surface with respect to the substrate and the variation in the inclination can be reduced.

本考案の実施例を以下に示す。第１図に於て１
はNiメツキを施したアルミダイカストからなる
パツケージケースであり、２は厚膜基板で、シリ
コン系接着剤でケースに接着されている。３がア
ルミパツドで、第２図に示すようにプレスによる
ダレ面３ａをボンデイング面とし、非ダレ面（つ
まりダレ面のない反対側の面）３ｂに半田メツキ
をして、半田付により厚膜基板２に固定されてい
る。４はヒートシンクでケース１に半田付されて
おり、５のトランジスタチツプはヒートシンク４
に半田付されている。そして、アルミパツドとト
ランジスタチツプ５との間をアルミワイヤ６でボ
ンデイングしている。 Examples of the present invention are shown below. 1 in Figure 1
2 is a package case made of die-cast aluminum plated with Ni, and 2 is a thick film substrate that is bonded to the case with a silicone adhesive. 3 is an aluminum pad, and as shown in Fig. 2, the sagging surface 3a caused by pressing is used as the bonding surface, and the non-sagging surface 3b (that is, the opposite surface without sagging) is soldered, and the thick film board is bonded by soldering. It is fixed at 2. 4 is a heat sink, which is soldered to case 1, and the transistor chip 5 is connected to heat sink 4.
is soldered to. Then, bonding is performed between the aluminum pad and the transistor chip 5 using an aluminum wire 6.

そこで、上記構成によると、前述したように、
非ダレ面３ｂの形状のばらつきが小さい事から、
ボンデイング面の基板に対する傾き、及びその傾
きのばらつきを低減できる。尚、アルミパツド３
のダレ面３ａを厚膜基板側にした場合、ボンデイ
ング装置のウエツジがパツドに接触することによ
りボンデイング強度が劣化するものが約３％程度
あるが、アルミパツド３の非ダレ面３ｂを厚膜基
板側にした場合はウエツジがパツドに接触するこ
とは皆無に等しいことが本考案者等の実験により
明らかになつている。 Therefore, according to the above configuration, as mentioned above,
Since the variation in the shape of the non-sag surface 3b is small,
The inclination of the bonding surface with respect to the substrate and the variation in the inclination can be reduced. In addition, aluminum pad 3
If the sagging surface 3a of the aluminum pad 3 is placed on the thick film substrate side, the bonding strength will deteriorate in about 3% of cases due to the wedge of the bonding device coming into contact with the pad. Experiments conducted by the present inventors have revealed that when this is done, there is almost no contact between the wedge and the pad.

以上述べた実施例では、トランジスタチツプ５
と厚膜基板２上のアルミパツド３のワイヤボンデ
イングのみ説明したが、本考案はアルミパツド間
のボンデイングにも適用できるし、厚膜基板以外
の所に位置するアルミパツドにも適用できること
は言うまでもない。 In the embodiment described above, the transistor chip 5
Although only the wire bonding of the aluminum pads 3 on the thick film substrate 2 has been described, it goes without saying that the present invention can also be applied to bonding between aluminum pads, and can also be applied to aluminum pads located in places other than the thick film substrate.

以上の述く本考案によれば、アルミパツドの非
ダレ面を厚膜基板側にすることにより、ボンデイ
ング面を厚膜基板と平行に保ち、かつボンデイン
グ装置のウエツジの面との平行度も確保できるた
め、ボンデイング条件が安定し、ボンデイングの
信頼性が向上するという効果が得られる。 According to the present invention described above, by placing the non-sag surface of the aluminum pad on the thick film substrate side, the bonding surface can be kept parallel to the thick film substrate and parallelism with the wedge surface of the bonding device can also be ensured. Therefore, the bonding conditions are stabilized and the bonding reliability is improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の概要を示すワイヤボンド部分
の側面図、第２図は本考案によるアルミパツドの
固定状態を示す断面図、第３図および第４図は従
来の不具合を説明するための図、第５図ａ及びｂ
は半田の表面張力の作用を説明する為のそれぞれ
従来及び本考案の断面図である。 １……パツケージケース、２……厚膜基板、３
……アルミパツド、３ａ……ダレ面、３ｂ……非
ダレ面、４……ヒートシンク、５……トランジス
タチツプ、６……アルミワイヤ。 Figure 1 is a side view of the wire bonding part showing the outline of the present invention, Figure 2 is a sectional view showing the fixed state of the aluminum pad according to the present invention, and Figures 3 and 4 are diagrams for explaining the conventional problems. , Figure 5 a and b
2A and 2B are cross-sectional views of the conventional and the present invention, respectively, for explaining the effect of surface tension of solder. 1...Package case, 2...Thick film substrate, 3
... Aluminum pad, 3a... Sagging surface, 3b... Non-sagging surface, 4... Heat sink, 5... Transistor chip, 6... Aluminum wire.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基板上にアルミニウム製パツドをはんだ付け
し、前記パツド上にアルミワイヤによりワイヤボ
ンドを実施して混成集積回路を構成する装置にお
いて、前記パツドの素材板からの打抜き等による
傾斜部分をもつダレ面をボンデイング面とし、前
記傾斜部分のない前記パツドの反対側の非ダレ面
を基板側にしてはんだ付けすることを特徴とする
混成集積回路装置。 In a device that configures a hybrid integrated circuit by soldering aluminum pads onto a substrate and wire-bonding the pads with aluminum wire, the sagging surface of the pad with an inclined portion is formed by punching the pad from a material plate, etc. 1. A hybrid integrated circuit device, wherein soldering is carried out with a non-sagging surface on the opposite side of the pad having no sloped portion as a bonding surface facing the substrate.
JP1981115225U 1981-07-31 1981-07-31 Hybrid integrated circuit device Granted JPS5820538U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981115225U JPS5820538U (en) 1981-07-31 1981-07-31 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981115225U JPS5820538U (en) 1981-07-31 1981-07-31 Hybrid integrated circuit device

Publications (2)

Publication Number Publication Date
JPS5820538U JPS5820538U (en) 1983-02-08
JPS6242536Y2 true JPS6242536Y2 (en) 1987-10-31

Family

ID=29909492

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981115225U Granted JPS5820538U (en) 1981-07-31 1981-07-31 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5820538U (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003031767A (en) * 2001-07-18 2003-01-31 Fuji Electric Co Ltd Semiconductor device

Also Published As

Publication number Publication date
JPS5820538U (en) 1983-02-08

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