JPS6242556A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6242556A
JPS6242556A JP18217585A JP18217585A JPS6242556A JP S6242556 A JPS6242556 A JP S6242556A JP 18217585 A JP18217585 A JP 18217585A JP 18217585 A JP18217585 A JP 18217585A JP S6242556 A JPS6242556 A JP S6242556A
Authority
JP
Japan
Prior art keywords
films
regions
semiconductor substrate
film
positions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18217585A
Other languages
Japanese (ja)
Inventor
Toshihiro Kuriyama
俊寛 栗山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP18217585A priority Critical patent/JPS6242556A/en
Publication of JPS6242556A publication Critical patent/JPS6242556A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)

Abstract

PURPOSE:To simplify a process by implanting the ions of a substance forming an insulator with the constitient atoms of a semiconductor substrate to the surface of the semiconductor substrate, to which an ion implantation stopping film is shaped selectively, and thermally treating the semiconductor substrate. CONSTITUTION:Ion implanting stopping films 6 are formed selectively to the surface of an Si substrate 1. The ions of oxygen are implanted. Consequently, oxygen atoms are distributed to considerably deep 3a positions from the surface in regions in which there is no film 6 while they are distributed at positions in the vicinity 3b of the surface in regions in which there are the films 6. Si oxide films are shaped at the positions of 3a and 3b through the application of heat treatment. As a result, regions 1a are insulated and isolated completely by the Si oxide films 3a, 3b. According to the method, the films 3a are shaped at a position deeper than the surface in the regions in which there is no film 6, thus eliminating the need for epitaxial growth on the formation of a device. The films 3b as element isolation regions are flattened approximately to the region 1a, thus making processesing time remarkably shorter than a groove isolating method, etc.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体装置特に5ilicon on In
5Jator(以下、SOIと呼ぶ)の製造方法に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to semiconductor devices, particularly 5 silicon on In
5 Jator (hereinafter referred to as SOI).

従来の技術 従来のSOIの製造方法を第2図を用いて簡単に述べる
。シリコン基板1の主表面に、酸素原子2を1o α 
 程度表面よりやや深い位置にイオン注入する(第2図
a)。次に、適当な熱処理を施こすと第2図すに示すよ
うに、表面よりやや深い所にシリコン酸化膜3が形成さ
れ、表面は、シリコン層1aが、わずかに保存される。
2. Description of the Related Art A conventional SOI manufacturing method will be briefly described with reference to FIG. Oxygen atoms 2 are placed on the main surface of the silicon substrate 1 at 1o α
The ions are implanted at a position slightly deeper than the surface (Fig. 2a). Next, when a suitable heat treatment is performed, a silicon oxide film 3 is formed slightly deeper than the surface, as shown in FIG. 2, and the silicon layer 1a is slightly preserved on the surface.

そして、前記シリコン層1&を種にして、エピタキシャ
ル層4を成長させる(第2図C)。次に、素子分離領域
5をシリコン酸化膜3に達する様に形成し、シリコン領
域4に、能動素子を形成するというものであった。
Then, using the silicon layer 1& as a seed, an epitaxial layer 4 is grown (FIG. 2C). Next, an element isolation region 5 was formed to reach the silicon oxide film 3, and an active element was formed in the silicon region 4.

発明が解決しようとする問題点 しかしながらこのような従来の構成では、工程が複雑で
コストが高くなるという問題点があった。
Problems to be Solved by the Invention However, such a conventional configuration has the problem that the process is complicated and the cost is high.

本発明はこのような問題点を解決するもので、工程を簡
略化することを目的とするものである。
The present invention solves these problems and aims to simplify the process.

一 問題を解決するだめの手段 この問題点を解決するために本発明の半導体装置の製造
方法は、シリコン基板の主表面にイオン注入阻止膜を選
択的に形成し、酸素原子をイオン注入阻止膜を十分貫通
するエネルギーでイオン注入し、熱処理を行うことから
構成される装置作  用 この構成により、注入した酸素原子のうち、イオン注入
阻止膜を貫通したものはシリコン基板のイオン 表面に分布し−ガご百人阻止膜のない基板に直接注入さ
れたものは、シリコン基板の表面からかなり深い位置に
分布するため、後の熱処理によって形成されるシリコン
酸化膜は、分離領域をも同時に形成するようになるので
、能動領域が完全に絶縁分離される。
Means for Solving the Problem In order to solve this problem, the method for manufacturing a semiconductor device of the present invention selectively forms an ion implantation blocking film on the main surface of a silicon substrate, and oxygen atoms are removed from the ion implantation blocking film. The device action consists of implanting ions with sufficient energy to penetrate the silicon substrate and performing heat treatment.With this configuration, of the implanted oxygen atoms, those that penetrate the ion implantation blocking film are distributed on the ion surface of the silicon substrate. If the material is directly implanted into a substrate without a barrier film, it will be distributed quite deep from the surface of the silicon substrate, so the silicon oxide film formed by subsequent heat treatment will also form an isolation region at the same time. Therefore, the active region is completely isolated.

実施例 第1図は本発明の一実施例によって製造されるSOIの
断面模式図であり、第1図において、1は、シリコン基
板、6は、イオン注入阻止膜、3a、3bは、シリコン
酸化膜である。以下に、第1図の構造のSOIの製造方
法を述べる。
Embodiment FIG. 1 is a schematic cross-sectional view of an SOI manufactured according to an embodiment of the present invention. In FIG. 1, 1 is a silicon substrate, 6 is an ion implantation blocking film, and 3a and 3b are silicon oxide It is a membrane. A method for manufacturing an SOI having the structure shown in FIG. 1 will be described below.

まず、シリコン基板1の表面に、厚さ1.5μmのシリ
コン酸化膜を成長させ、選択的にエツチングを行なうこ
とによりイオン注入阻止膜6を形成する。次に、IMe
Vの加速エネルギーで1018crn−2程度の酸素を
イオン注入する0すると、イオン注入阻止膜6のない領
域では、酸素原子は、表面からかなり深い3aの位置に
分布し、一方イオン注入阻止膜6の存在する領域では、
表面近傍の3bの位置に分布するようになる。その後、
適当な熱処理を加えてやれば、3a、3bの場所にシリ
コン酸化膜が形成される。その結果、表面のシリコン領
域1&は、シリコン酸化膜3a、3bで完全に絶縁分離
される。そして、酸素原子は、イオン注入阻止膜6を貫
通させるだけの高いエネルギーで注入されるため、イオ
ン注入阻止膜6の存在しない領域では、表面より深い位
置にシリコン酸化膜3とが形成されるため、能動領域と
なるシリコン領域1aの厚さは0.5μmぐらい得られ
、デバイスを形成する上で、従来例で行なっていたエピ
タキシャル成長を行なう必要がなくなる。また、素子分
離領域となるシリコン酸化膜3bは、シリコン領域1a
とほぼ平坦になるため、溝分離法などと比べると大幅な
工程短縮となる。
First, a 1.5 μm thick silicon oxide film is grown on the surface of the silicon substrate 1, and selectively etched to form the ion implantation blocking film 6. Next, IMe
When oxygen ions of about 1018 crn-2 are ion-implanted with an acceleration energy of V, in the region where the ion-implantation blocking film 6 is not present, oxygen atoms are distributed at a position 3a considerably deep from the surface, while in the region where the ion-implantation blocking film 6 is In the area where
It comes to be distributed at position 3b near the surface. after that,
By applying appropriate heat treatment, a silicon oxide film is formed at the locations 3a and 3b. As a result, the silicon region 1& on the surface is completely insulated and isolated by the silicon oxide films 3a and 3b. Since oxygen atoms are implanted with enough energy to penetrate the ion implantation blocking film 6, the silicon oxide film 3 is formed at a position deeper than the surface in the region where the ion implantation blocking film 6 does not exist. The thickness of the silicon region 1a serving as the active region is approximately 0.5 .mu.m, and there is no need to perform epitaxial growth, which was performed in the conventional example, when forming a device. In addition, the silicon oxide film 3b serving as the element isolation region is formed in the silicon region 1a.
Since the surface is almost flat, the process is significantly shortened compared to methods such as groove separation.

また、シリコン領域1aの厚さはイオン注入阻止膜6の
材料および膜厚と注入エネルギーの組み合せを変えるこ
とで変えることができる。
Furthermore, the thickness of the silicon region 1a can be changed by changing the combination of the material and thickness of the ion implantation blocking film 6 and the implantation energy.

なお、本実施例では、注入イオンは、酸素としたが、窒
素でもよく、その場合は、絶縁物は、シリコンナイトラ
イドとなり同様な効果が得られることは言うまでもない
In this embodiment, oxygen was used as the implanted ion, but nitrogen may also be used. In that case, the insulator becomes silicon nitride, and it goes without saying that similar effects can be obtained.

発明の効果 以上のように本発明は、イオン注入阻止膜が選択的に形
成された半導体基板の表面に、半導体基板の構成原子と
絶縁物を形成する物質をイオン注入することにより、従
来法に比べ、エピタキシャル成長工程および素子分離工
程を省略でき、しかも、素子分離領域と能動領域が平坦
となるなどその実用的効果は犬なるものがある0
Effects of the Invention As described above, the present invention improves the conventional method by ion-implanting a substance that forms an insulator with the constituent atoms of the semiconductor substrate into the surface of a semiconductor substrate on which an ion implantation blocking film is selectively formed. In comparison, the epitaxial growth process and element isolation process can be omitted, and the practical effects are outstanding, such as the element isolation region and active region are flattened.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例により製造されたSOIの断
面模式図、第2図は従来のSOIの製造工程断面図であ
る。 1.4・・・・・・シリコン基板、1a・・・・・・シ
リコン領域、2・・・・・・イオン注入阻止膜、3a、
3b、6・・・・・・シリコン酸化膜、4a・・・・・
・シリコン層、6・・・・・・酸素原子、7・・・・・
・エピタキシャル層、8・・・・・・分離領域。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第 
 1  図                1−一−
シ9ル基稙6−−恢ン辻入7!L+1:膜 f−一゛ンリコン暮1遁 5−一一分4g9臀慝
FIG. 1 is a schematic cross-sectional view of an SOI manufactured according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a conventional SOI manufacturing process. 1.4...Silicon substrate, 1a...Silicon region, 2...Ion implantation blocking film, 3a,
3b, 6...Silicon oxide film, 4a...
・Silicon layer, 6...Oxygen atoms, 7...
-Epitaxial layer, 8... Separation region. Name of agent: Patent attorney Toshio Nakao and 1 other person
1 Figure 1-1-
Shi9ru Motoki 6--Tsujiiri 7! L + 1: Membrane f - 1 ゛ single life 1 release 5 - 11 minutes 4g 9 buttocks

Claims (1)

【特許請求の範囲】[Claims] 半導体基板の主表面にイオン注入阻止膜を選択的に形成
する工程と、前記半導体基板の主たる構成原子とで絶縁
物を形成する物質を、前記イオン注入阻止膜を十分貫通
するエネルギーで、イオン注入する工程と、半導体基板
の主たる構成原子とイオン注入原子を結合させる熱処理
工程とを有することを特徴とする半導体装置の製造方法
A step of selectively forming an ion implantation blocking film on the main surface of the semiconductor substrate, and ion implantation of a substance that forms an insulator with the main constituent atoms of the semiconductor substrate with enough energy to penetrate the ion implantation blocking film. 1. A method of manufacturing a semiconductor device, comprising: a step of bonding main constituent atoms of a semiconductor substrate with ion-implanted atoms.
JP18217585A 1985-08-20 1985-08-20 Manufacture of semiconductor device Pending JPS6242556A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18217585A JPS6242556A (en) 1985-08-20 1985-08-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18217585A JPS6242556A (en) 1985-08-20 1985-08-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6242556A true JPS6242556A (en) 1987-02-24

Family

ID=16113651

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18217585A Pending JPS6242556A (en) 1985-08-20 1985-08-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6242556A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4935029A (en) * 1972-08-03 1974-04-01
JPS5662333A (en) * 1979-10-26 1981-05-28 Toshiba Corp Mos type semiconductor memory device and production thereof
JPS5745947A (en) * 1980-09-03 1982-03-16 Toshiba Corp Mos type semiconductor integrated circuit
JPS59208851A (en) * 1983-05-13 1984-11-27 Hitachi Ltd Semiconductor device and manufacture thereof
JPS61269329A (en) * 1985-05-23 1986-11-28 Matsushita Electronics Corp Manufacture of semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4935029A (en) * 1972-08-03 1974-04-01
JPS5662333A (en) * 1979-10-26 1981-05-28 Toshiba Corp Mos type semiconductor memory device and production thereof
JPS5745947A (en) * 1980-09-03 1982-03-16 Toshiba Corp Mos type semiconductor integrated circuit
JPS59208851A (en) * 1983-05-13 1984-11-27 Hitachi Ltd Semiconductor device and manufacture thereof
JPS61269329A (en) * 1985-05-23 1986-11-28 Matsushita Electronics Corp Manufacture of semiconductor device

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