JPS624367A - Bibolar semiconductor device - Google Patents

Abstract

PURPOSE:To increase the junction capacitance of the collector-base with a small element area and to attain high integration, high reliability and high speed, by forming the base-collector junction vertically along a trench reaching the buried layer from the base region. CONSTITUTION:After an N-type buried layer 11, an N-type epitaxial layer 13 and an element-separating oxide film 12 are formed on a P-type semiconductor substrate 10, a silicon oxide film 12A and a silicon nitride film 22 are formed on the region for the element to be formed, and a trench 24 reaching the epitaxial layer 13 is formed using photo resist 23 as a mask. After removing the photo resist 23, a P-type diffusion layer 14 is formed in the trench 24 and the trench 24 is etched using the nitride film 22 as a mask till it reaches the buried layer 11. An N-type diffusion layer 15 shallower than the P-type diffusion layer 14 is formed inside the trench and the trench is filled with polycrystalline silicon 18 having N-type impurities doped. Next, P-type impurities are ion- implanted to form a base region 16, and an N-type emitter region 17 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bipolar semiconductor device, and particularly to a bipolar semiconductor device having a junction capacitance between a collector and a base for use on a memory.

[Conventional technology]

A bipolar memory semiconductor device requires a speed-up capacitor to increase the speed, or a capacitor between the collector and the base to ensure reliability against alpha rays.

FIG. 3 is a cross-sectional view of a conventional bipolar semiconductor device. In order to increase the capacitance, the area of the base region 160 is increased, and the impurity concentration of the base region 16 and the epitaxial layer 13, which is the collector region, is increased. I was doing it.

[Problem that the invention seeks to solve]

However, the above-mentioned conventional technology has the disadvantage that the area of the transistor is large, and that if the concentration is increased without changing the area, the withstand voltage between the collector and the base deteriorates.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bipolar semiconductor device that eliminates the above-mentioned drawbacks and provides a large collector-to-base junction capacitance with a relatively small area.

[Means for solving problems]

The bipolar semiconductor device of the present invention includes a buried layer of an opposite conductivity type formed on a semiconductor substrate of one conductivity type and an epitaxial layer of an opposite conductivity type formed on the buried layer as a collector region,
A bibo type 2 semiconductor device comprising a base region of one conductivity type formed on the epitaxial layer and an emitter region of opposite conductivity type formed on the base region, wherein a groove is provided extending from the base region to the buried layer. A first diffusion layer of the opposite conductivity type connected to the buried layer is provided on the side surface of this groove, and a second diffusion layer of one conductivity type connected to the base region is provided outside the first diffusion layer. This is provided with reverse conductivity type polycrystalline silicon connected to the electrode.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of an embodiment of the present invention.

In FIG. 1, an N-type buried W is formed on a P-type semiconductor substrate IO.
A P-type base region 16 and an N-type emitter region 17 are formed on this epitaxial layer 13. Then, the epitaxial layer 13 is penetrated and buried 7111
A groove 24 reaching up to
A P-type diffusion IM 14 connected to 6 is provided. Furthermore, in the groove 24, there is connected to the collector electrode 21C and 7=jN.
A type polycrystalline silicon 18 is buried therein.

In the Bibo 2 type semiconductor device formed in this way, the PN junction corresponding to the base-collector junction is also formed by the P-type around @24 and the 8-base diffusion/1lt14, 15, so the The capacitance can be made extremely large without significantly increasing the element area.

Next, an example of the backdoor method of this embodiment will be explained using FIG. 2 (FIG. 2(f)).

First, as shown in FIG. 2(a)K, an N-type buried fill, an N-type epitaxial layer 13, and an element isolation oxide film 12 are formed on a semiconductor substrate 10 using the conventional technique, and then a silicon oxide film is formed in an element region. The film 12A and the silicon nitride film 22 are grown, and the oxide film 1 is grown using the photoresist 23 as a mask.
2A, the nitride film 22 and epitaxial layer 13 are etched to form a groove 24. At this time, the depth of the groove 24 is kept within epitaxial /1113.

Next, as shown in FIG. 2(b), the photoresist 23 is removed and a P-type diffusion layer t#14 is formed inside the groove. Next, as shown in FIG. 2(c), the epitaxial layer 13 is etched using the nitride layer 22 as a mask until the groove reaches the buried layer 11.

Next, in Fig. 2 (as shown by the mountain), there is a Pa diffusion layer 1 inside the groove.
4, a shallow Nya diffusion layer 15 is formed. Subsequently, polycrystalline silicon doped with N-type impurities is deposited, and anisotropic processing and etching are further performed to leave polycrystalline silicon 18 only inside the groove. Next, as shown in FIG.
is in contact with the P-type diffusion chamber 14.

Next, as shown in the 211th (fl), openings corresponding to the base electrode and emitter electrode are formed, polycrystalline silicon is grown, and the N-type emitter region 17 and the graft base layer are formed using polycrystalline silicon 19.20. Finally, aluminum for wiring is deposited and patterned to form electrodes 21, thereby obtaining the bipolar semiconductor device of this embodiment shown in FIG.

In this # structure, since the base and collector junctions are formed in the vertical direction along the groove 24, the area occupied by the element on the substrate can be reduced in proportion to the large capacitance.

Incidentally, in the above embodiment, a case was explained in which Q and P type semiconductor substrates were used, but it goes without saying that an Na+ conductor substrate may also be used.

〔Effect of the invention〕

As explained above, according to the present invention, with a small element area,
A bipolar transistor with a large collector-base junction capacitance can be realized, and a bipolar semiconductor device capable of high integration, high reliability, and high speed can be obtained.

[Brief explanation of drawings]

FIG. 1 is a sectional view of an embodiment of the present invention, and FIGS. 2(a) to (
f) is a process cross-sectional view for explaining a manufacturing method according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view for explaining a conventional bipolar semiconductor device. lO...P-type semiconductor substrate, 11...N
Mold buried layer, 12... Element isolation oxide film, 13...
...Epitaxial layer, 14...P type diffusion layer, 15...N type diffusion layer, 16...Base region, 17...Emitter, area, 18.19
...Nu polycrystalline silicon, 20...P
Type polycrystalline silicon, 21.21B, 21E, 2IC...
····electrode. Nest I @ Early 2 Figure 2 Figure 3 Pi

Claims (1)

[Claims] A buried layer of opposite conductivity type formed on a semiconductor substrate of one conductivity type and an epitaxial layer of opposite conductivity type formed on the buried layer are used as a collector region, and a base of one conductivity type formed on the epitaxial layer is used as a collector region. In a bipolar semiconductor device comprising a reverse conductivity type emitter region formed on the base region and a reverse conductivity type emitter region formed on the base region, a groove extending from the base region to the buried layer is provided, and a side surface of the groove is connected to the reverse conductivity type emitter region. the first of
A second diffusion layer of one conductivity type connected to the base region is provided outside the first diffusion layer, and polycrystalline silicon of opposite conductivity is provided in the groove to be connected to the collector electrode. A bipolar semiconductor device characterized by: