JPS6244701B2 - - Google Patents

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Publication number
JPS6244701B2
JPS6244701B2 JP54094143A JP9414379A JPS6244701B2 JP S6244701 B2 JPS6244701 B2 JP S6244701B2 JP 54094143 A JP54094143 A JP 54094143A JP 9414379 A JP9414379 A JP 9414379A JP S6244701 B2 JPS6244701 B2 JP S6244701B2
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JP
Japan
Prior art keywords
layer
thickness
oxide
silicon
polysilicon
Prior art date
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Expired
Application number
JP54094143A
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English (en)
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JPS5518099A (en
Inventor
Shuwaabe Ururitsuhi
Yakopusu Eruin
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Siemens Corp
Original Assignee
Siemens Corp
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Publication of JPS5518099A publication Critical patent/JPS5518099A/ja
Publication of JPS6244701B2 publication Critical patent/JPS6244701B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/8314—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having gate insulating layers with different properties
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01342—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid by deposition, e.g. evaporation, ALD or laser deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/83138—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having different shapes or dimensions of their gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/141—Self-alignment coat gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/156—Sonos

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Description

【発明の詳細な説明】 この発明はMNOSトランジスタとMOSトラン
ジスタを自己整合式に重なり合つたポリシリコン
接触と共に一つの共通基板上に製作する方法に関
するものである。ここでMNOSトランジスタはメ
モリ素子として使用され、窒化シリコン層の酸化
によつて作られる酸化層が障壁層として使用され
る。
特に記憶回路用のMOSデバイスの製作には現
在ポリシリコンゲート技術が有利であるとされて
いる。ポリシリコン技術では電界効果トランジス
タのゲート電極およびこの電極の接続導体に多結
晶シリコンが使用されている。これによりゲート
電極とその接続導体をアルミニウムで作る場合に
比べてゲートソース間およびゲートドレン間の重
り合いによる容量が極めて小さくなり更にポリシ
リコンの形で補助の導体路面が存在するという利
点が得られる。
MNOS形デバイスはゲート誘電体が窒化シリコ
ン（Si3N4）層と二酸化シリコン（SiO2）層から成
る二重層である点でMOS形デバイスと異つてい
る。MNOS技術は電気的にプログラム組替え可能
のROMに応用されている。このメモリはメモリ
セル毎に一つのトランジスタだけを必要とするた
め小形であつて集積密度を高くすることができ
る。
IEEE Transactions on Electron Deveces、
ED―24〔５〕p.584（1977）にはシリコン・ゲー
トMNOS構造がＰシリコン基板に作られたキヤパ
シタンスを例として記載されている。この場合窒
化シリコン層表面を酸化して作られた酸窒化層が
蓄積情報の崩壊又はその部分的消去の原因となる
シリコン・ゲート電極からのキヤリヤ注入を阻止
する。この層を以後障壁層と呼ぶことにする。
この発明はこの発見をEAROM（電気的に書替
え可能のROM）の製作に利用し同時にできるだ
け集積密度の高いメモリ回路をできるだけ少数の
工程で製作する問題を解決しようとするもので特
許請求の範囲第１項に特徴として挙げた工程を採
用することによつて所期の目的が達成される。
この発明の方法によればメモリ窒化物層の形成
後に第二の局部的酸化物層として作用し又周辺ト
ランジスタのゲート酸化物層となる酸化物層を作
ることにより従来のゲート酸化が窒化物析出前に
行われるシリコン・ゲートMNOS構造の場合と比
べてマスク形成工程が省略される。これによつて
失敗の原因となる工程数が低下し歩留りが上昇す
る。その上この工程に要する時間と費用が省かれ
る。
図面に示した実施例についてこの発明を更に詳
細に説明する。第１図乃至第６図にこの発明によ
るｎ―チヤネルMNOSメモリセルの製造過程を示
す。第１図に示すように（100）面に沿つて切ら
れたｐシリコン結晶基板１１を出発材料としてこ
れに能動トランジスタ領域を分離するための構造
を持つSiO2層１２をイソプレーナ法によつて作
る。その際ｐ基板１１をまず厚さ100nmの酸化シ
リコン層で覆い、その上に200nm厚さの窒化シリ
コン層を設ける。この層に構造を作つた後シリコ
ン基板表面部分を酸化して厚膜酸化物として作用
する1000nm厚さのSiO2層１２を作る。続いて窒
化シリコン層を除去して第２図に示すように全面
に3nm厚さのトンネルオキサイドとして作用する
SiO2層１３を析出させる。その上にメモリ窒化
層１４と２４を約50nmの厚さにつけ、マスク技
術によりメモリトランジスタ１４の領域と後で作
られるポリシリコン金属接触の形成個所２４だけ
に残された構造とする。
第３図に示すようにゲート酸化物１５として作
用する厚さ50nmのSiO2層を設け、その際窒化シ
リコン層の表面を厚さ約20nmの酸窒化層１６に
変える。酸窒化層の代りに障壁層として作用する
SiO2層を設けてもよい。
続いて第４図に示すように厚さ約500nmのポリ
シリコン層１７を析出させそれに構造を作る。図
を見易くするため両SiO2層１３と１５は一つの
層１５として示してある。第４図に点破線Ｃでか
こんだ区域はメモリトランジスタの一部分であ
り、点破線Ｄでかこんだ区域は通常のトランジス
タの区域である。
次にソース・ドレン領域とするため第５図の矢
印１８で示すように例えば150kevのAS+イオン
を５×1015cm-2の表面密度で注入しn+領域１９を
作る。イオン注入後の回復処理を行つた後中間酸
化物層２０を500nmの厚さにつけこれに接触孔を
設けるため第６図に示す構造を作る。金属マスク
を使用して接触孔区域に接触金属層２１を設けた
後全体を保護酸化物マスク例えばリン酸塩ガラス
で覆う。上記の製作過程から分るようにメモリ窒
化層の後でゲート酸化層を作ることにより通常の
シリコンゲートMNOS法と比べて一つのマスク処
理工程が省かれる。ポリシリコン層が酸化された
メモリ窒化層の上に重ねられることにより（第４
図の区域Ｃ）絶縁層の厚さに差を生じスプリツ
ト・ゲート構造となりドレン基板間の破壊放電が
阻止され動作の安全性が高くなる。
ポリシリコン―金属接触のためのポリシリコン
領域１７は厚膜酸化物１２の上で通常のように
SiO2上にはなく、Si3N4層上にある。窒化物層２
３，１６はエツチストツプとして作用するから接
触孔２１（第６図中央）のエツチングに際してポ
リシリコン１７の回り込みエツチングは発生しな
い。これによつて特大の接触孔を持つ自己整合式
ポリシリコン接触形成の可能性が生ずる。
第７図に第６図のＡ―Ｂ線に沿断面を示す。破
線２２でかこんだ区域は自己整合式の重なり合つ
た接触であり、この巨大な接触孔を持つ自己整合
接触によりメモリ回路の集積密度を著しく高める
ことができる。その他の部分は第１図乃至第６図
の図符号部分に対応する。矩形２３でかこんだ区
域はLOCOS法で作られた盆地であり、区域２５
は接触孔を示している。
【図面の簡単な説明】
第１図から第６図まではこの発明によるメモリ
セルの製造過程を示す断面図、第７図は完成品の
正面図である。各図において１１は基板、１２と
１３はSiO2層、１４と２４は窒化シリコン層、
１５はゲート酸化物層、１６は酸窒化物層、１７
はポリシリコン層、２０は中間酸化物層、２１は
金属層である。

Claims (1)

  1. 【特許請求の範囲】 １ 次の工程： (a) 半導体基板１１の上に能動トランジスタ領域
    ２３の分離のために構造を持つSiO2層１２を
    LOCOS法又はイソプレーナ法で作る； (b) 全面酸化によりトンネルオキサイドとして作
    用するSiO2層１３を作る； (c) メモリトランジスタ区域Ｃと重なり合い接触
    の区域に構造化された窒化シリコン層１４，２
    ４を作る； (d) ゲート酸化層１５の酸化形成と同時に窒化シ
    リコン層表面１４を障壁層として作用する酸窒
    化層に変える； (e) 全面的にポリシリコン層１７を析出させ続い
    てこのポリシリコン層に構造を作る； (f) ソース・ドレン領域１９を作る； (g) 中間酸化物として作用する二酸化シリコン層
    ２０を析出させる； (h) ソース・ドレン領域１９と厚い酸化物１２の
    上のポリシリコン層に向かつての接触孔２５を
    作る； (i) 全面的に金属層２１を析出させこれに構造を
    作る； に従つて行われることを特徴とするMNOSトラン
    ジスタとMOSトランジスタを自己整合式に重な
    り合うポリシリコン接触と共に一つの共通基板上
    に製作する方法。 ２ 工程段(b)においてトンネルオキサイドとして
    作用するSiO2層１３が1.5nm乃至12nmの厚さに
    調整され、工程段(C)においてその上に作られる窒
    化シリコン層１４，２４が20nm乃至60nmの厚さ
    に調整されることを特徴とする特許請求の範囲第
    １項記載の方法。 ３ 工程段(d)の酸化処理によりゲート区域には厚
    さ50乃至100nmの酸化層１５が作られ、窒化シリ
    コン層１４の表面には厚さ５乃至30nmの酸化層
    １６が作られることを特徴とする特許請求の範囲
    第１項又は第２項記載の方法。 ４ 工程段(e)におけるポリシリコン層１７が100
    乃至1000nmの厚さに析出することを特徴とする
    特許請求の範囲第１項乃至第３項のいずれか１項
    に記載の方法。 ５ 工程段(f)においてソース・ドレン領域１９が
    イオン注入によつて作られることを特徴とする特
    許請求の範囲第１項乃至第５項のいずれか１項に
    記載の方法。 ６ 比抵抗が２乃至20Ωcmのｐ型シリコン基板を
    出発材料として工程段(f)におけるｎ型ドープ領域
    １９が面密度１×1015乃至１×1016cm-2、イオン
    エネルギー20乃至300keVのAs+イオン注入によ
    つて作られることを特徴とする特許請求の範囲第
    １項乃至第５項のいずれか１項に記載の方法。
JP9414379A 1978-07-24 1979-07-24 Method of manufacturing multiple insulating layer memory cell integrated circuit Granted JPS5518099A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2832388A DE2832388C2 (de) 1978-07-24 1978-07-24 Verfahren zum Herstellen von MNOS- und MOS-Transistoren in Silizium-Gate-Technologie auf einem Halbleitersubstrat

Publications (2)

Publication Number Publication Date
JPS5518099A JPS5518099A (en) 1980-02-07
JPS6244701B2 true JPS6244701B2 (ja) 1987-09-22

Family

ID=6045194

Family Applications (1)

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JP9414379A Granted JPS5518099A (en) 1978-07-24 1979-07-24 Method of manufacturing multiple insulating layer memory cell integrated circuit

Country Status (5)

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US (1) US4257832A (ja)
JP (1) JPS5518099A (ja)
DE (1) DE2832388C2 (ja)
FR (1) FR2432216A1 (ja)
GB (1) GB2026768B (ja)

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Also Published As

Publication number Publication date
DE2832388C2 (de) 1986-08-14
JPS5518099A (en) 1980-02-07
GB2026768B (en) 1982-11-03
US4257832A (en) 1981-03-24
GB2026768A (en) 1980-02-06
FR2432216B1 (ja) 1982-12-10
FR2432216A1 (fr) 1980-02-22
DE2832388A1 (de) 1980-02-14

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