JPS6266331A - Memory device - Google Patents

Abstract

PURPOSE:To suppress branching when a user program is executed by suppressing the specification of a branching circuit regardless of the specification and specifying the operation of an increment circuit side forcibly. CONSTITUTION:When a normal operation mode signal is inputted to an input terminal 7 and a normal instruction is executed, a branch control circuit 4 is switched to the side of the increment circuit 3 and a program counter 2 enters increment operation. When a branch instruction is executed, on the other hand, the branch control circuit 4 is switched to the side of the branching circuit 5 on the basis of the judgement of a branch condition judging circuit 8 with a branch suppressing function and the counter 2 sets an address value supplied from the branching circuit 5. When a branch suppressing operation mode signal is inputted, the circuit 8 suppresses branching by switching the branch control circuit 4 to the side of the increment circuit 3 only in executing an instruction word stored in a specific address of an instruction memory 1 according to the contents of the counter 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device, and in particular, an instruction memory for storing instruction words is addressed based on an address signal from a program counter, and a desired instruction word is stored in the memory device. The present invention relates to improvements in memory devices for reading .

[Prior Art] FIG. 2 is a schematic block diagram of a conventional memory device. First, the configuration of a conventional memory device will be described with reference to FIG. The instruction memory 1 stores a plurality of instruction words. The address of this instruction memory 1 can be specified by the 1!1 number output of the program counter 2. Then, the program counter 2 updates its count output by 1 every time a signal is input from the increment circuit 3 via the branch control circuit 4. Further, the address value from the branch circuit 5 is set in the program counter 2 when the branch control circuit 4 is switched to the branch circuit 5 side. The branch control circuit 4 is switched to the increment circuit 3 side or the branch circuit 5 side based on the judgment output of the branch condition judgment circuit 6.

Next, the operation will be explained. When executing a normal instruction, the branch condition determination circuit 6 switches the branch control circuit 4 to the increment circuit 3 side. As a result, the program counter 2 increases the count value of A by 1 each time a signal is input from the increment circuit 3, and the instruction memory 1
Specify the address and read the predetermined instruction word. on the other hand,
When executing a branch instruction, the branch condition determination circuit 6 determines the branch instruction and switches the branch control circuit 4 to the branch circuit 5 side. Thereby, the address value output from the branch circuit 5 is set in the program counter 2.

[Problems to be solved by the invention] Since the conventional memory device is configured as described above,
When running a normal user program to perform a functional test, there are repetitive loops caused by branches, so
There was a problem in that the same instruction word was executed many times and the functional test took time.

Generally, when performing a functional test, it is desirable to execute a wide variety of commands in as short a time as possible, and the execution of a user program using a conventional memory device has the disadvantage that it is not suitable for functional testing.

Therefore, a main object of the present invention is to provide a memory device that can perform operations suitable for functional testing using a user program by forcibly controlling the execution of the user program.

[Means for Solving the Problems] A memory device according to the present invention uses a program counter to address an instruction memory that stores instruction words, and updates the address value of the program counter using an increment circuit or an address setting circuit. In the case where the branch circuit specifies whether to set the address value by the branch circuit, the specification is suppressed and the branch suppress-1 circuit forcibly specifies the operation on the increment circuit side, regardless of the specification of the branch circuit. This is what I did.

[Operation] The memory device according to the present invention ignores and executes the branch instruction of the user program by setting an operation mode that prevents the branch instruction from branching, and as a result, the memory device that is programmed in the user program It is possible to execute all of the many different types of instructions that are available, and no repetitive loops occur, so there is no need to execute many specific instructions.
It is possible to perform operations suitable for functional tests using user programs.

[Embodiment of the Invention] FIG. 1 is a block diagram of an embodiment of the invention. In the embodiment shown in FIG. 1, a branch condition judgment circuit 8 with a branch suppression function is used instead of the branch condition judgment circuit 6 shown in FIG.
The branch condition determination circuit 8 with branch suppression function is provided with an input terminal 7 for inputting a branch suppression operation mode signal, and the other branch memory 1, program counter 2, increment circuit 3, The branch control circuit 4 and branch circuit 5 are the same as those shown in FIG. 2 described above.

Next, the operation will be explained. When the normal operation mode signal is input to the input terminal 7, the same operation as described above with reference to FIG. 2 is performed. That is, the branch control circuit 4 is switched to the increment circuit 3 side, and the program counter 2 updates the address value based on the signal from the increment circuit 3 to designate the address of the instruction memory 1.

On the other hand, when executing a branch instruction or the like, the branch control circuit 4
is switched to the branch circuit 5 side. Thereby, the program counter 2 sets the address value given from the branch circuit 5, and specifies the address of the instruction memory 1 based on the address value.

When the branch suppression operation mode signal is applied to the input terminal 7,
A branch condition determination circuit 8 with a branch suppression function determines whether or not to perform branch suppression according to the contents of the program counter 2. In other words, only when executing the instruction word stored at a specific address in the instruction memory 1, it is determined that the branch suppression condition is satisfied, and the input of the branch control circuit 40 is forced to the increment circuit 3 side. By specifying this, branching is suppressed. FIG. 1 shows a state when a branch suppression operation mode signal is applied to the input terminal 7 and an instruction word at a specific address in the instruction memory 1 to be branch suppressed is executed, and the input to the branch control circuit 4 is Regardless of the execution result of the instruction, branching is suppressed because it is always executed from the increment circuit 3 side.

As described above, by providing the branch condition determination circuit 8 with branch suppression function and the input terminal 7, the branch suppression function can be realized.
Branching can be inhibited only for instruction words stored at specific addresses. Therefore, the user program stored at a specific address in the instruction memory 1 can be executed without repeating a loop, and the functionality of the memory storage can be tested in a short time using the user program.

In the above-described embodiment, the branch condition determination circuit 8 with a branch suppression function determines whether or not branch suppression is to be performed by applying a branch suppression operation mode signal to the input terminal 7. It is also possible to provide an instruction word for branch suppression control, and when this instruction word is read out, the branch condition judgment circuit 8 with branch suppression function makes a judgment, and as a result, performs the branch suppression function. In that case,
The input terminal 7 can be omitted.

[Effects of the Invention] As described above, according to the present invention, regardless of the specification of a branch circuit, the specification can be suppressed and the operation of the increment circuit side can be forcibly specified, so that the user program cannot be executed. It is possible to suppress branching when executing a program, suppress repetitive loops, and execute a wide variety of instruction words in a short time when performing functional tests using user programs.
Functional tests can be easily performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. Second
The figure is a block diagram of a conventional ME-E IJ system. In the figure, 1 is an instruction memory, 2 is a program counter, 3 is an increment circuit, 4 is a branch control circuit, 5 is a branch circuit, 7 is an input terminal, 8 is a branch suppression function, and 4 is a branch condition judgment circuit.

Claims (4)

[Claims] (1) an instruction memory for storing instruction words; a program counter for specifying the address of the instruction word to be executed among the instruction words stored in the instruction memory; and a program counter for specifying the address of the instruction word to be executed among the instruction words stored in the instruction memory; an increment circuit; an address setting circuit for setting a predetermined address value in the program counter; a branch for specifying to operate either updating of the address value by the increment circuit or setting of the address value by the address setting circuit; A memory device comprising a circuit and a branch suppression circuit for suppressing the specification and forcibly specifying an operation on the side of the increment circuit regardless of the specification of the branch circuit. (2) The branch suppression circuit operates only on instruction words stored at a specific address among the instruction words stored in the instruction memory. memory device. (3) The memory device according to claim 1, further comprising an input terminal for receiving a control signal for controlling the branch suppression and applying it to the branch suppression circuit. (4) providing a command word for controlling the branch suppression;
A memory device according to claim 1.