JPS6270445U - - Google Patents

Info

Publication number
JPS6270445U
JPS6270445U JP1985162182U JP16218285U JPS6270445U JP S6270445 U JPS6270445 U JP S6270445U JP 1985162182 U JP1985162182 U JP 1985162182U JP 16218285 U JP16218285 U JP 16218285U JP S6270445 U JPS6270445 U JP S6270445U
Authority
JP
Japan
Prior art keywords
back surface
external lead
lead terminals
board
extended
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985162182U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985162182U priority Critical patent/JPS6270445U/ja
Publication of JPS6270445U publication Critical patent/JPS6270445U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Cooling Or The Like Of Electrical Apparatus (AREA)

Description

【図面の簡単な説明】
第1図は本考案の一実施例の断面図、第2図は
従来例の断面図である。 1,1′……配線基板、2……金属パターン(
裏面)、3,3′……外部リード端子、4……半
田、5……ペレツトコート樹脂、6……ICペレ
ツト、7……端子、8,8′……基板裏面取付部
分。

Claims (1)

    【実用新案登録請求の範囲】
  1. 配線基板裏面に、外部リード端子にそれぞれ対
    応した分離領域を有する金属パターンを設け、前
    記外部リード端子の基板裏面取付部分を延長して
    、前記金属パターンにそれぞれ連結していること
    を特徴とする混成集積回路装置。
JP1985162182U 1985-10-22 1985-10-22 Pending JPS6270445U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985162182U JPS6270445U (ja) 1985-10-22 1985-10-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985162182U JPS6270445U (ja) 1985-10-22 1985-10-22

Publications (1)

Publication Number Publication Date
JPS6270445U true JPS6270445U (ja) 1987-05-02

Family

ID=31089201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985162182U Pending JPS6270445U (ja) 1985-10-22 1985-10-22

Country Status (1)

Country Link
JP (1) JPS6270445U (ja)

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