JPS628032B2 - - Google Patents
Info
- Publication number
- JPS628032B2 JPS628032B2 JP55006001A JP600180A JPS628032B2 JP S628032 B2 JPS628032 B2 JP S628032B2 JP 55006001 A JP55006001 A JP 55006001A JP 600180 A JP600180 A JP 600180A JP S628032 B2 JPS628032 B2 JP S628032B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor
- sealing
- glass member
- protrusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W42/00—Arrangements for protection of devices
- H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W42/25—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons against alpha rays, e.g. for outer space applications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
- H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置に関し、特にその外囲器
（パツケージ）の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to the structure of its envelope (package).
一般に半導体装置は、たとえびセラミツクある
いはコバールなどの支持台上に半導体素子を固着
し、その半導体素子を、たとえばセラミツクなど
の壁部材および蓋部材などを用いて封入してい
る。 Generally, in a semiconductor device, a semiconductor element is fixed on a support base made of ceramic or Kovar, and the semiconductor element is enclosed using a wall member made of ceramic, a lid member, and the like.
この封入されるべき半導体素子が高密度の集積
回路、特にMOS型半導体素子や電荷転送デバイ
ス（CCD）などで構成される場合、外囲器構成
部材特に封止材からの放射線照射、特にα線照射
により半導体素子に例えば記憶情報の破壊等の特
性劣化（ソフトエラー）を生ずる恐れがある。 When the semiconductor element to be encapsulated is composed of a high-density integrated circuit, especially a MOS type semiconductor element or a charge transfer device (CCD), radiation irradiation from the envelope components, especially the encapsulant, especially α-rays may occur. Irradiation may cause characteristic deterioration (soft errors) such as destruction of stored information in semiconductor elements.
これは、自然界に存在し放射性崩壊する際にα
線を生ずるウラニウム（Ｕ）あるいはトリウム
（Th）等の放射性同位元素が、前記封止材として
の低融点ガラスや鉛と錫から成るソルダーの中に
含まれていることによる。尚、上記同位元素は外
位器を構成するセラミツク材の中にも含まれてい
るが、極めて微量であり実質的な影響は及ぼさな
い。 This exists in the natural world and when radioactively decays, α
This is because radioactive isotopes such as uranium (U) or thorium (Th) that generate lines are contained in the low-melting glass or solder made of lead and tin as the sealing material. Although the above-mentioned isotope is also contained in the ceramic material constituting the external device, it is in an extremely small amount and has no substantial effect.
発生されたα線は半導体素子内に侵入すると、
正孔と電子の対を発生し、該正孔ああるいは電子
のいずれかが該半導体素子内の活性領域に注入さ
れて、例えば前述の如く記憶情報の破壊を招く。
従つて、該半導体素子において活性領域が形成さ
れている半導体基板表面領域へのα線の照射、侵
入の防止を図ることが重要であり、前記外囲器に
あつて一般に該半導体素子の表面付近に位置する
封止材から発生するα線の抑制が必要となる。 When the generated alpha rays enter the semiconductor element,
Pairs of holes and electrons are generated, and either the holes or electrons are injected into the active region within the semiconductor device, leading to destruction of stored information, for example, as described above.
Therefore, it is important to prevent alpha rays from irradiating and penetrating the surface area of the semiconductor substrate where the active region is formed in the semiconductor element. It is necessary to suppress alpha rays generated from the sealing material located in the area.
本発明は前述の点に鑑みてなされたもので、そ
の目的は半導体素子表面への放射線照射、特にα
線照射を遮へいして、α線照射による半導体素子
の特性冷化を防止する構造を有してなる半導体装
置を提供することにある。 The present invention has been made in view of the above-mentioned points, and its purpose is to irradiate the surface of a semiconductor element with radiation, particularly α
An object of the present invention is to provide a semiconductor device having a structure that blocks ray irradiation and prevents characteristic cooling of a semiconductor element due to alpha ray irradiation.
このため本発明によれば、半導体素子と該半導
体素子を収容固着する収容部を有する収容容器
と、該収容容器の封止部に封止材により固着され
た該半導体素子を気密封止する蓋部材とを備えた
半導体装置において、前記収容容器の前記封止部
と前記収容部との間に該収容部より高く、且つ該
封止部に被着される封止材の高さより高い突部を
設けてなることを特徴とする半導体装置が提供さ
れる。 Therefore, according to the present invention, there is provided a storage container having a semiconductor element, a storage part for housing and fixing the semiconductor element, and a lid for hermetically sealing the semiconductor element fixed to the sealing part of the storage container with a sealing material. a protrusion between the sealing part of the housing container and the housing part, which is higher than the housing part and higher than the height of the sealing material applied to the sealing part; Provided is a semiconductor device characterized by being provided with.
以下本発明を図面をもつて詳細に説明しよう。 Hereinafter, the present invention will be explained in detail with reference to the drawings.
第１図は本発明の第１の実施例を示す。 FIG. 1 shows a first embodiment of the invention.
同図において、１１はセラミツク材から構成さ
れる素子収容容器本体、１２は該素子収容容器１
１のほぼ中央に収容固着された半導体記憶素子等
の半導体素子である。また１３は素子収容容器１
１にガラス部材１４により固着され、アルミニウ
ム等からなるリード線１５により前記半導体素子
１２の電極と電気的に接続されるコバール等から
なる外部接続端子であり、１６は前記ガラス部材
１４により素子収容容器１１に固着され、前記半
導体素子１２を気密封止するセラミツク又は金属
材より構成される蓋（キヤツプ）である。 In the figure, reference numeral 11 denotes an element housing container body made of ceramic material, and 12 denotes the element housing container 1.
A semiconductor device such as a semiconductor memory device is housed and fixed approximately in the center of the device. 13 is an element storage container 1
An external connection terminal made of Kovar or the like is fixed to the glass member 14 by a glass member 14 and is electrically connected to the electrode of the semiconductor element 12 by a lead wire 15 made of aluminum or the like. 11 and hermetically seals the semiconductor element 12, the cap is made of ceramic or metal.
かかる半導体素子封入構造は、一般にサーデイ
ツプ型を称される。 Such a semiconductor element encapsulation structure is generally referred to as a cerdip type.
そして本発明によれば、素子収容容器本体１１
の半導体素子１２固着部とガラス部材１４との間
に突起１１１を配設する。該突起１１１の高さ
は、ガラス部材１４の最大厚さ以上の高さとす
る。 According to the present invention, the element housing container body 11
A protrusion 111 is disposed between the fixed portion of the semiconductor element 12 and the glass member 14. The height of the protrusion 111 is greater than the maximum thickness of the glass member 14.
このような構造によれば、封止部材をも兼ねる
ガラス部材１４と、半導体素子１２とは突起１１
１により遮へいされる。したがつて、ガラス部材
１４から放射されるα線等の放射線は半導体素子
１１へ到達することができず、当該半導体素子に
ソフトエラーを生じない。また突起１１１は、外
部接続端子１３の固着の際その位置決めを行うの
に有利であり、更に封止の際ガラス部材１４の半
導体素子側への流動を阻止する、
なお、このような突起１１１を有する素子収容
容器本体は、セラミツク材（グリーンシート）の
プレス加工あるいは多層構造化によつて形成する
ことができる。 According to such a structure, the glass member 14 which also serves as a sealing member and the semiconductor element 12 are connected to the protrusion 11.
1. Therefore, radiation such as α rays emitted from the glass member 14 cannot reach the semiconductor element 11, and no soft errors occur in the semiconductor element. Further, the protrusion 111 is advantageous in positioning the external connection terminal 13 when it is fixed, and furthermore, it prevents the glass member 14 from flowing toward the semiconductor element side during sealing. The element storage container main body can be formed by pressing a ceramic material (green sheet) or forming a multilayer structure.
第２図は、本発明の第２の実施例を示す。前記
第１図に示す実施例と同一部位には同一番号を付
している。 FIG. 2 shows a second embodiment of the invention. The same parts as in the embodiment shown in FIG. 1 are given the same numbers.
本実施例にあたつては、突起１１２が特にガラ
ス部材１４すなわち封止部の近傍に位置して高く
配設される。このような構造によれば、ガラス部
材１４から放射される放射線の半導体素子１２へ
の到達を阻止し得るうえに、半導体素子１２の表
面と外部接続端子１３のリード線１５の接続部と
をほぼ同一の水平面に配設することができ、リー
ド線の接続を容易に行うことができる。 In this embodiment, the protrusion 112 is located particularly near the glass member 14, that is, the sealing portion, and is disposed at a high height. According to such a structure, radiation emitted from the glass member 14 can be prevented from reaching the semiconductor element 12, and the surface of the semiconductor element 12 and the connection part of the lead wire 15 of the external connection terminal 13 can be substantially connected. They can be arranged on the same horizontal plane, and lead wires can be easily connected.
以上のように本発明による構造を有して成る半
導体装置は、従来のパツケージング工程に何ら変
更を加えることなく容易に半導体装置の製造に適
用することができ、外囲器構成部材の特に封止材
からの半導体素子表面へのα線照射を遮断して、
半導体素子のα線照射による特性劣化の防止が可
能となり、さらに封止工程における封止材の流れ
込みも抑える効果があり、半導体装置の信頼性向
上に極めて有効である。 As described above, the semiconductor device having the structure according to the present invention can be easily applied to the manufacturing of semiconductor devices without making any changes to the conventional packaging process. By blocking alpha ray irradiation from the stopper material to the semiconductor element surface,
It is possible to prevent characteristic deterioration of semiconductor elements due to alpha ray irradiation, and it is also effective in suppressing the flow of sealing material during the sealing process, which is extremely effective in improving the reliability of semiconductor devices.
第１図及び第２図は、それぞれ本発明による半
導体装置の実施例の構造を示す断面図である。
図において、１１……素子収容容器本体、１２
……半導体素子、１３……外部接続端子、１４…
…ガラス部材、１５……リード線、１６……蓋、
１１１，１１２……突起。
1 and 2 are cross-sectional views showing the structure of an embodiment of a semiconductor device according to the present invention, respectively. In the figure, 11...Element storage container main body, 12
...Semiconductor element, 13...External connection terminal, 14...
... Glass member, 15 ... Lead wire, 16 ... Lid,
111,112...Protrusion.
Claims (1)
収容部を有する収容容器と、該収容容器の封止部
に封止材により固着され該半導体素子を気密封止
する蓋部材とを備えた半導体装置において、 前記収容容器の前記封止部と前記収容部との間
に該収容部より高く、且つ該封止部に被着される
封止材の高さより高い突部を設けてなることを特
徴とする半導体装置。[Scope of Claims] 1. A storage container having a semiconductor element, a storage part that houses and secures the semiconductor element, and a lid member that is fixed to the sealing part of the storage container with a sealing material and hermetically seals the semiconductor element. In the semiconductor device, a protrusion is provided between the sealing part of the housing container and the housing part, which is higher than the housing part and higher than the height of the encapsulant applied to the sealing part. A semiconductor device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP600180A JPS56103452A (en) | 1980-01-22 | 1980-01-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP600180A JPS56103452A (en) | 1980-01-22 | 1980-01-22 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56103452A JPS56103452A (en) | 1981-08-18 |
| JPS628032B2 true JPS628032B2 (en) | 1987-02-20 |
Family
ID=11626510
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP600180A Granted JPS56103452A (en) | 1980-01-22 | 1980-01-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56103452A (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4839716A (en) * | 1987-06-01 | 1989-06-13 | Olin Corporation | Semiconductor packaging |
| US5635754A (en) * | 1994-04-01 | 1997-06-03 | Space Electronics, Inc. | Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages |
| US6613978B2 (en) | 1993-06-18 | 2003-09-02 | Maxwell Technologies, Inc. | Radiation shielding of three dimensional multi-chip modules |
| US5880403A (en) | 1994-04-01 | 1999-03-09 | Space Electronics, Inc. | Radiation shielding of three dimensional multi-chip modules |
| US6261508B1 (en) | 1994-04-01 | 2001-07-17 | Maxwell Electronic Components Group, Inc. | Method for making a shielding composition |
| US6720493B1 (en) | 1994-04-01 | 2004-04-13 | Space Electronics, Inc. | Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages |
| US6455864B1 (en) | 1994-04-01 | 2002-09-24 | Maxwell Electronic Components Group, Inc. | Methods and compositions for ionizing radiation shielding |
| US6368899B1 (en) | 2000-03-08 | 2002-04-09 | Maxwell Electronic Components Group, Inc. | Electronic device packaging |
| US7382043B2 (en) | 2002-09-25 | 2008-06-03 | Maxwell Technologies, Inc. | Method and apparatus for shielding an integrated circuit from radiation |
| US7191516B2 (en) | 2003-07-16 | 2007-03-20 | Maxwell Technologies, Inc. | Method for shielding integrated circuit devices |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5149810Y2 (en) * | 1971-02-25 | 1976-12-01 | ||
| JPS5652415A (en) * | 1979-10-03 | 1981-05-11 | Hitachi Ltd | Temperature control unit |
-
1980
- 1980-01-22 JP JP600180A patent/JPS56103452A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56103452A (en) | 1981-08-18 |
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