JPS6282437A - Control system for interruption of debug in information processor - Google Patents

Abstract

PURPOSE:To acquire a desired request to start an interrupt for debugging while reproducing the same state as actual circumstance by controlling the start of the interrupt for debugging in accordance with contents of write data with respect to a write request to a specific address of a memory. CONSTITUTION:A command and an address sent to a main storage device 3 from a memory access control part 2 through a signal line 201 are compared with comparison information held in a comparison command and address register 4 by a comparing circuit 6. Write data sent from the memory access control part 2 to the main storage device 3 through a signal line 202 is compared with comparison information held in a comparison data register 5 by a comparing circuit 7. When the debugging mode is set, an input signal line 104 of an AND gate 8 is set to '1', and comparison coincidence signal s601 and 701 are checked, and an output 801 is sent to an operation control part 1 as a control signal for the start of the interrupt for debugging.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to a control method for debug interrupts in an information processing device.

[Conventional technology]

2. Description of the Related Art Conventionally, in information processing devices, debugging work has been carried out by focusing on memory access operations in order to analyze malfunctions caused by logical mistakes in programs or hardware failures. Conventionally, for such debugging work, a special register is used to set the type of memory request to be detected and the access address. hardware support was provided to detect when a debug interrupt condition occurred and report it to software.

[Problem that the invention seeks to solve]

Such conventional debugging methods are fully useful when accessing a specific address in memory itself is an operation directly related to the problem to be debugged.

However, if there are multiple accesses to that particular address (1), a debug interrupt can be reported for any of them, so it is important to check whether this is actually a meaningless case or not. It is necessary to make a judgment within the debug interrupt processing routine.This judgment is performed, for example, when an attonos match is reported in a write request to memory, what value was the attonos data rewritten to? This is an important decision +
It is often 41. Although it is possible to check such data using software, if the desired case occurs, it is easy to operate the processing of the extra dehasogging interrupt, which is generated in normal mode. The problem is that the debugging function is not used effectively in the debug mode, and the debugging function is not used effectively.

The purpose of the present invention (4) is to make it possible to capture a desired request and activate a dehasog interrupt while reproducing the same state as the actual environment.

[Means for solving problems]

In order to achieve the object of the present invention, the first comparison information holding means holds comparison information regarding commands and addresses of memory requests, and the second comparison information holding means holds comparison information regarding write data. and a first comparing means for comparing the command and address of a memory request generated in the information processing device with the comparison information held in the first comparison information holding means; a second comparison means for comparing the generated write data and the comparison information held in the second comparison holding means; and a predetermined comparison result between the first comparison means and the second comparison means. A debugging interrupt activation means is provided which generates a control message for activating the debugging interrupt when the debugging interrupt is obtained.

[Effect]

The first comparison information holding means holds the write command as the command type and the specific address as the address, and the second comparison information holding means holds the comparison data.1! , the debug interrupt generating means is the first
If a debug interrupt is activated when a match is detected by both the first comparison means and the second comparison means, the same data as the above comparison data will be written to a specific address. A debug interrupt is triggered when a memory request occurs.

The debug interrupt activation means uses the first comparison means to match the matching power (+
If the debug interrupt is activated when the second comparison means does not detect a match, the debug interrupt can be activated when data other than the comparison data at a specific address is written. Can be started.

〔Example〕

The figure is a block diagram of main parts of an information processing device according to an embodiment of the present invention, in which 1 is an arithmetic control unit including all main circuits for controlling and executing arithmetic operations, 2 is inside the arithmetic control unit 1,
A memory access control unit having an interface with the main storage device 3; 4 a comparison command/address register for holding comparison information with actual memory access commands and addresses; 5 a memory access control unit for use when the memory access is a write command; A comparison data register 6 holds comparison information with actual write data, and a comparison data register 6 compares the command and address sent from the memory access control unit 2 to the main storage device 3 through the signal line 201 and is held in the command/address register 4. A comparison circuit 7 is used to compare the write data sent from the memory access control unit 2 to the main storage device 3 through the Shinzuki cotton 202 with the comparison information held in the comparison data register 5. The comparison circuit 8 is an AND gate. An output 801 of this AND gate 8 is sent to the arithmetic control section 1 as a control signal for activating a debug interrupt.

The activation of the dehasog interrupt in the information processing apparatus of this embodiment is controlled as follows.

Suppose now that the memory request to be detected is a write command, and that we want to cause a debug interrupt only when a specific address is rewritten to a specific data pattern that is known in advance. For example, when you run a certain program, this kind of thing can be identified by a special pattern that would never occur in the first place! This is effective when a phenomenon occurs in which the contents of the /space are disturbed, and this is one of the events that conventionally takes a very long time to debug.

When performing a debug interrupt as described above, first, the command of the memory request to be detected by the program and the address value to be accessed are stored as comparison information in the comparison command/address register 4 via the signal line 101. The data pattern is stored as comparison information in the comparison data register 5 via the signal line 102.

Then, by setting the debug mode, the input signal lines 104 of the anime games 1 and 8 are set to "1", and thereafter, the comparison match signals 601 and 701 are started to be checked by the comparison 4NR6+7. At this time, in order to enable the operation of the comparator circuit 7, the signal line 103 is set to "1" as specified by the program.

In the above state, start executing the program in question. Even under normal conditions, this program cannot use the comparison command.
Writing is performed to the address set in the address register 4, but if the data sent to that address from the memory access control unit 2 via the signal wire 202 is normal, the data is written to the address set in the comparison data register 5. Since there is no match, the output 801 of the AND gate 8 is "0", and no extra debugging interrupt is generated. Therefore, the same environment as would occur in normal operating mode without setting debug mode is guaranteed. On the other hand, when a desired memory request occurs, that is, in this case, an unexpected routine writes abnormal data (a specific data pattern to a specific address), the outputs 601 and 701 of the comparison circuit 6.7 are both becomes “1” and gate 8
A debugging interrupt is generated by the output 801, and it becomes possible to obtain valuable information for identifying program bugs or hardware failures.

In the embodiment described in "-", the comparator circuit 7 is configured so that when it detects a match between the data written to the main memory 3 and the data held in the comparison data register 5, the output 01 becomes "1", and the comparison circuit 7 The debug interrupt is activated when the same data as the information is written, but for example, when the comparison circuit 7
When detecting a mismatch, the output cuff 01 is set to "1", or the input signal line 7 of the AND gate 8
By configuring the signal on 01 to be inverted and input to AND gate 8, a debug interrupt will be activated when a specific address is destroyed with a value other than the originally expected specific value. It can also be configured as follows.

In addition, if the memory request command is a read command, by setting the signal line 103 to 0 and setting the output cuff 01 of the comparison circuit 7 to 1 regardless of the data,
A data interrupt can be generated depending only on the state of the output of the comparison circuit 6.

〔Effect of the invention〕

As explained above, the present invention controls the activation of a dehasog interrupt according to the content of the write data regarding a write request to a specific address in memory, thereby allowing the desired request to be executed while reproducing the same state as the actual environment. It becomes possible to capture and activate a debugging interrupt, which has the effect of improving debugging efficiency.

[Brief explanation of drawings]

The figure is a block diagram of main parts of an information processing device according to an embodiment of the present invention. In the figure, 1 is an arithmetic control unit, 2 is a memory access control unit, 3 is a main memory, 4 is a comparison command/address register, 5 is a comparison data register, 6.7 is a comparison circuit, and 8
is an AND gate, and 801 is a control signal for activating a data interrupt.

Claims (1)

[Claims] First comparison information holding means for holding comparison information regarding commands and addresses of memory requests; second comparison information holding means for holding comparison information regarding write data; a first comparing means for comparing a command and address of a memory request with comparison information held in the first comparison information holding means; and write data generated in the information processing device and the second comparison information holding means. a second comparing means for comparing comparison information held in the first comparing means, and generating a control signal for activating a debug interrupt when a predetermined comparison result is obtained by the first comparing means and the second comparing means. 1. A debug interrupt control method for an information processing device, comprising a debug interrupt activation means for activating a debug interrupt.