JPH03135111A - Output buffer circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION OBJECTS OF THE INVENTION (Field of Industrial Application) The present invention relates to an output buffer circuit, and is particularly used for an output buffer circuit provided in a semiconductor integrated circuit.

(Prior Art) An example of an output buffer circuit using a conventional IC is shown below. The output buffer circuit in FIG. 9 connects a P-channel Mos transistor TPOI whose source is connected to the vDD power supply and GND.
N-channel Mos with source connected to (ground) potential
The drains of the transistors TNOI are commonly connected and connected to the output line 13, the gates of both transistors are commonly connected,
CMOS inverter IVOI connected to signal input line 2o
Consisting of FIG. 10 shows input and output waveforms when the output buffer channel shown in FIG. 9 operates. FIG. 11 shows an example of the output buffer circuit of the CMOS inverter shown in FIG.
The polysilicon PGOI and NGOI forming the gate of the S transistor TNOI are connected to the input line 2 by metal wiring.
They are connected together by 0.

Here, in the output buffer circuit shown in FIG.
Due to the resonant circuit consisting of O1, LO2, LO3 and the load capacitance cO1 of the output line 13, voltage oscillations occur in the power supply lines 11, 12 and the output line 13 when the output buffer is driven, and as shown in FIG. Shoot and undershoot phenomena occur. Furthermore, as in the pattern shown in FIG. 11, when polysilicon gates divided into several parts are connected together by metal wiring 20, all the connected transistors (To1 to TO6 or T11 to T16 ) are turned on at the same time, the output load is rapidly charged and discharged, resulting in the above-mentioned overshoot and
The undershoot phenomenon becomes more and more noticeable. As a result, the power supply voltage fluctuates, and the output buffer circuit described above
There is a problem in that it induces malfunctions and latch-up phenomena in other elements connected to the power supply line.

Fig. 12 is an example of the output buffer circuit using the CMOS inverter shown in Fig. 9 configured using another pattern. In the output buffer circuit shown in Fig. 12, in order to take advantage of gate delay, the divided gates are connected in series using polysilicon PGO2 and NGO2, which are gate electrode materials, instead of being connected all at once using metal wiring. Therefore, the CR of the polysilicon gate is
Due to the delay, the P-channel, N-channel MOS transistors (T21 to T26 or T31
~T36) are no longer turned on at the same time, and in the P-channel MOS transistor, T21-T22...T
7, and in the case of an N-channel MOS transistor, it gradually turns on as T31-T32...T, so the charge accumulated in the load capacitance cO1 flows into GND and the load in FIG. YongjiicO1's VD
Since charging is performed slowly due to the inflow of current from the D power source, the above-mentioned overshoot and undershoot phenomena are suppressed. However, in the output buffer circuit shown in FIG. 12, the delay due to the gate CR is determined by the gate dimensions of the transistor, so if you want to obtain a predetermined amount of gate delay, the P-channel MOS constituting the output buffer The size of the transistor and N-channel MOS transistor must be adjusted, but here the MO
In S transistors, the output current value per unit size of an N-channel MOS transistor is 2 to 2 to 2 times higher than that of a P-channel MOS transistor when the transistor size is the same due to differences in mobility in the same process.
This becomes about three times as large, and the setting of the transistor size with respect to the required transistor characteristics becomes unbalanced between P-channel and N-channel transistors, making it difficult to adjust the transistor size to obtain a predetermined amount of gate delay. In addition, with the miniaturization of devices due to recent advances in semiconductor technology, the layer resistance of polysilicon, which has been conventionally used as a gate electrode material, has increased to 20 to 30 Ω/. This is high and causes slow wiring. Therefore, silicide, a high-melting point metal, is being used as a new gate material, and Mo
S i2 , WS i2 .

The layer resistance when TaSi2 is used as the gate electrode is 2
~3Ω/mouth, which is an order of magnitude smaller than that of polysilicon. The chemical properties of these silicides are very similar to that of polysilicon, and with the exception of some steps, they can be handled in the same manner as polysilicon.

In this way, when trying to reduce the layer resistance of the gate electrode material with the miniaturization of devices, using the delay of the gate electrode material as shown in the output buffer in Figure 12, we can reduce the layer resistance that occurs in the output signal during output buffer switching. Even if an attempt is made to suppress the overshoot and undershoot phenomena that occur, it will be impossible to achieve this goal.

(Problems to be Solved by the Invention) As described above, as the speed of semiconductor devices increases, in conventional output buffer circuits, as shown in FIG. 9, parasitic inductance due to wiring and load capacitance of output lines cause When switching the output buffer, the power line,
Voltage oscillations occur in the output line, causing overshoot and undershoot phenomena as shown in Figure 10, resulting in fluctuations in the power supply voltage, which may cause malfunctions and latch-up phenomena in other elements connected to the same power supply line. It was causing the trigger.

In addition, in the circuit shown in FIG. 12, which was devised to improve the above-mentioned problem, the transistor used for the output buffer is gradually turned on using the delay caused by the CR of the gate electrode material, so that the transistor connected to the output line of the output buffer is not connected to the output line of the output buffer. Since the load capacity is charged and discharged slowly, overshoot and undershoot phenomena are suppressed. However, it may be difficult to adjust the transistor size to obtain a predetermined amount of gate delay. Furthermore, if the delay due to the CR of the gate electrode is large, the period during which the transistors TPO1 and TNOI in FIG. 9 are simultaneously turned on becomes long, and a large through current flows between the power supplies VDDSGND and VDDSGND. In addition, in recent years, with the miniaturization of devices due to advances in semiconductor technology, the resistance of gate electrode materials has been reduced. Even if attempts are made to suppress the shoot and undershoot phenomena, it is impossible to achieve this goal.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an output buffer circuit that can improve the above-mentioned conventional problems.

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides (1) a P-channel MO whose outputs are commonly connected;
Each gate of the S transistor and the N channel MOS transistor is divided into a plurality of parts, and the gates of the divided P channel MOS transistors are connected by a first resistance element, and the gates of the N channel MOS transistors are connected by a first resistance element. This is an output buffer circuit characterized by connecting two resistive elements. The present invention also provides (2) the first and second
The output buffer circuit according to (1) above is characterized in that a diffusion layer is used as the resistance element. The present invention also provides (3) the above-mentioned first aspect. As the second resistance element, the first . The output buffer circuit according to (1) above is characterized in that a second delay circuit is used.

That is, in the present invention, by dividing the transistor gate of the output buffer and connecting the gates with a resistor element, the transistor can be turned on gradually, so that the load capacitance connected to the output line can be gradually charged and discharged. It can be carried out. Furthermore, by configuring the resistance element with a transistor set to a predetermined size, it is possible to reduce the through current generated during output buffer switching. Therefore, the present invention suppresses overshoot and undershoot phenomena that occur during output buffer switching in conventional output buffers as semiconductor devices increase in speed, and prevents through current between the power supply and ground during output buffer switching. Therefore, it is possible to prevent malfunctions and latch-up phenomena of other elements that share the power supply.

In addition, in the present invention, even if the resistance of the gate electrode is lowered due to the miniaturization of devices due to recent advances in semiconductor technology, the resistance element provided between the divided gate electrodes allows the first
The problem described in FIG. 2 does not occur.

(Example) Examples of the present invention are shown below. 1 to 8 are pattern image circuit diagrams representing embodiments of the present invention. In FIG. 1, the gate of the P-channel transistor TP01 of the output buffer is divided into PC11 to PG14, and the resistance elements DFOI to DFOI by diffusion layers are connected between adjacent gates.
Connected from DFO3, N-channel transistor TNOI
The gates of are divided into NGII to N013, and adjacent gates are connected by resistance elements DF11 and DF12 using diffusion layers.The sources S of each are commonly connected on the power supply side, and the drains D of each are connected to the output line 42. are commonly connected.

In this circuit, the output 41 of a pre-buffer I V 1.0 by a CMOS inverter, to which the input 40 is connected, is first applied to the gate 11.0 of a P-channel transistor. It is connected to the N-channel transistor gate NGII, and then T41→
'1''42→T43→...T48, T51→T52→T53→...T5 in N channel transistor
6, the load capacitor CO1 connected to the output line 42 is gradually charged and discharged. This causes the overshoot in Figure 10.

The undershoot phenomenon is suppressed. In addition, in the configuration shown in Figure 1, in which the divided gates are connected by resistive elements, the delay amount can be set appropriately, and the resistance value of the diffusion layer is usually 50 to 100Ω1.
Since it is approximately 0 and variable depending on the shape of the diffusion layer pattern, it is easy to set it to obtain a predetermined gate delay amount.

FIG. 2 shows a different embodiment of the invention. In this embodiment, the gates of the P-channel transistors of the output buffer are divided into 13 parts PCII to PG14, and the gates of the N-channel transistors are divided into 13 parts, NGII to N. Adjacent gates are commonly connected to the input side and the output side, respectively. P-channel transistors (TPII to TP13 on the P-channel side, TP14 and TP15 on the N-channel side) whose gates are given a potential of ND (ground) and VDDg at their gates.
N-channel transistors (TN11 to TN13 on the P-channel side, TM14.TM on the N-channel side)
01), and the gm (conductance) of each of the P-channel transistors TP11 to TP13 connecting the gates of the P-channel transistor TPOI is the same as that of the P-channel transistor connecting the gates of the N-channel transistor TNOI. Transistor TP 14~TP
15, and the gm of each of the N-channel transistors TN14 to TN15 connecting the gates of the N-channel transistor TNOI is greater than the gm of each of the N-channel transistors TN11 to TN13 connecting the gates of the P-channel transistor TPOI. gm
is set larger. The respective drains D are commonly connected by an output line 42, and the input point 4
The output 41 of the pre-buffer IVIO by the CMOS inverter of 0 is connected to the P-channel transistor T of the output buffer.
11 and N channel transistor T at the gate P of POI
It is connected to the gate NG11 of NOI.

In the circuit of Fig. 2, input point 40 of input IN is set to VDD.
When the potential of the node 41 is lowered from the GND potential to the GND potential, the P-channel transistor of the CMOS inverter IV10 is turned on, and the potential of the node 41 starts to rise from the GND potential. Next, in the output buffer, the potentials of its gates PGII and NGII begin to rise. In the P-channel transistor, P-channel transistors TP11 to TP13 connecting between each divided gate are turned on.
Channel transistors 741-748 are quickly turned off to prevent through current.

After this, the N-channel transistor TNO1 of the output buffer
In this case, the transistors 751 to T56 are gradually turned on by turning on the N channel transistors TN14 to TN15 connecting the divided gates. At this time, N channel transistors TN14 to TN
The on-resistance of 15 is the N-channel transistor 753.
As the gate potential of ~T56 rises, it increases due to the back gate bias effect, and the rise in the gate potential becomes gradual. In addition, transistors TP14 and TP
15 serves to finally bring the gate potential to a complete "1" level. Next, contrary to the above, the signal input node 40
When increasing from GND potential to VDD potential, CMOS
The N-channel transistor of inverter IVIO is turned on, and the potential of node 41 begins to fall from the VDD potential. Next, in the output buffer, its gate PGI 1
, N11 begins to fall, and in the N-channel transistor TNOI, the N-channel transistors TN14 and TM01 that connect the divided gates are turned on, and the N-channel transistors T51 to T5 are turned on.
6 is quickly turned off and can prevent through current. Thereafter, in the P-channel transistor TPOI of the output buffer, the P-channel transistors TPII-TP13 connecting the divided gates are turned on, and the transistors T41-T48 are gradually turned on.

At this time, the on-resistance of the P-channel transistors TP11 to TP13 is equal to the on-resistance of the P-channel transistors 743 to T48.
As the gate potential decreases, it increases due to the back gate bias effect, and the increase in the gate potential becomes gradual. Further, the transistors TNII to TN13 function to finally bring the gate potential to a complete "0" level.

FIG. 3 shows a different embodiment of the invention. In FIG. 3, the gates of the P-channel transistors of the output buffer are divided into PC11 to PG14, and the gates of the N-channel transistors are divided into NGII to N013. P-channel transistors TP11 to TP13 whose output sides are commonly connected and whose gates are supplied with input IN
The N-channel transistors are connected using N-channel transistors TNII to TN13 whose gates are given a VDD potential, and the gates of the N-channel transistors are connected to P transistors whose input and output sides are respectively commonly connected and whose gates are given a GND potential.
channel transistors TP14, TP15 and an N-channel transistor TN whose gate is supplied with input IN;
14. The gm of each of the P-channel transistors TP11 to TP13 that connects the gates of the P-channel transistors is the same as that of each of the P-channel transistors TP14 and TP15 that connects the N-channel transistors. gm, and the gm of each of the N-channel transistors TN14 and TM01, which connect the gates of the N-channel transistors, is P
It is set larger than the gm of each of the N-channel transistors TN11 to TN13 connecting the gates of the channel transistors.

The respective drains D are commonly connected by an output line 42, and the output 41 of the pre-buffer IVIO by the CMOS inverter with the node 40 as the input point is connected to the gate PGII of the P-channel transistor and the gate NGII of the N-channel transistor of the output buffer. It is connected to the.

Now, when the signal input IV is lowered from the VDD potential to the GND potential in the circuit shown in FIG. The potentials of gates PG11 and NG11 begin to rise.

In the P-channel transistor TPOI, the P-channel transistor TPOI connects each divided gate.
A "0" level is applied to the gates of PII to TP13, and when these transistors are turned on, the P channel transistors 741 to 748 are rapidly turned off. After this, the N-channel transistor TNO of the output buffer
In I, P connecting between each divided gate
By turning on channel transistors TP14 and TP15, transistors 751 to T56 are gradually turned on. At this time, N-channel transistors TN14, T
Since the "0° level of the input node 40 is applied to the gate of M01, TM14 and TM01 are in the off state.Next, contrary to the above, the signal input IN is raised from the GND potential to the VDD potential. Then, CMOS inverter IVI
The N-channel transistor at node 41 turns on.
The potential begins to drop from the VDD potential, and in the output buffer, the potentials of gates PG11 and NG11 begin to fall. In the N-channel transistor TNOI, the N-channel transistors TN14 and TM01, which connect the divided gates, have their gates connected to the input node 40.
1” level is given, and by turning on these transistors, the N-channel transistors T51 to T5
6 turns off quickly.

Then the P-channel transistor TPOI of the output buffer
In , the transistors T41 to 748 are gradually turned on by turning on the N channel transistors TN11 to TN13 connecting between the respective divided gates. At this time, P channel transistors TP11 to T
Since the "1m level" of the input node 40 is applied to the gate of P13, TP11 to TP13 are in the off state.

FIG. 4 shows a different embodiment of the invention. Here, the gate of the P-channel transistor TPO1 of the output buffer is connected to PC.
II to PC; 14, N-channel transistor TNOI
The gate of the P-channel transistor is divided into NGII to N013, and the gate side of the P-channel transistor is connected to VD.
N-channel transistor TN21 to which D potential is applied
Connected by TN23 and divided gates PG12
~PG141. : connects the drains of P-channel transistors TP21 to TP23 whose gates are connected to the input point 4o and whose sources are connected to the output 41 of the inverter IVIO.

The gate side of the N-channel transistor TNOI is connected to the P-channel transistors TP24 and TP25 whose gates are given GNDTIi level, and the respective divided gates NG12 and NG13 are connected to the input point 40 at the gate and connected to the inverter at the source. The drains of N-channel transistors TN24 and TN25 connected to the output 41 of IVIO are connected to each other. The gm of each of the P-channel transistors TP21 to TP23 is TP24,
larger than that of TP25, and the gm of each of the N-channel transistors TN24 and TN25 is T21 to TN2.
It is set larger than that of 3. The drains of the transistors 741 to 748 and 751 to T56 are commonly connected by an output line 42, and are pre-buffered by a CMOS inverter whose input point is the node 40.
The output 41 of N10 is connected to the gate PG11 of the P-channel transistor and the gate NG11 of the N-channel transistor of the output buffer.

Now, in the circuit of FIG. 4, the signal input node 40 is connected to VD.
When lowering the potential from D7@ level to GND potential, the inverter I
The P-channel transistor of VIO is turned on, and the potential of node 41 begins to rise from GND. In the P-channel transistor TPOI of the output buffer, TP
Since the "0° level" of the input point 40 of 21 to TP23 is applied, when these transistors turn on, the P channel transistors 741 to 748 quickly turn off.After this, the N channel transistor TNO1 of the output buffer The transistors T51 to T56 are gradually turned on depending on when the P channel transistors TP24 and TP25 connecting between the divided gates are turned on.At this time, the N channel transistor TN24 is turned on.
, TN25 are in an off state because the "0" level of the gate input node 40 is applied. Next, contrary to the above,
When the signal input node 40 is raised from the GND potential to the VDD potential, the N-channel transistor of the CMOS inverter IVIO is turned on, and the potential of the node 41 begins to fall from VDD. In the N-channel transistor TNO1 of the output buffer, the transistor TN24
, TN25 are given the "1" level at the input point 40, so when these transistors are turned on, the N-channel transistors 751 to T56 are quickly turned off. Thereafter, in the P-channel transistor TPOI of the output buffer, the N-channel transistors TN21-TN23 connecting the divided gates are turned on, so that the transistors T41-748 are gradually turned on. At this time, P channel transistor TP2
1 to TP2B are in an off state because the "1" level of the input node 40 is applied to their gates.

In the embodiments shown in FIGS. 2 to 4 above, the on-resistance value of the transistor can be freely set by changing the gm of the transistor used as a resistance element. As shown in the example, by setting the gm of each transistor used as a resistance element to a predetermined value, charging and discharging (switching) of the off-side transistor gate can be made faster during output buffer switching, and charging and discharging (switching) of the on-side transistor gate can be made faster. By slowing down the discharge,
The through current flowing between VDD, output buffer P channel transistor TPOI, output buffer N channel transistor TNO1 and GND during switching is reduced.

FIG. 5 shows a modification of FIG. 2, in which the pre-buffer section is composed of an N-channel transistor TI and a P-channel transistor T2. These transistors are controlled by the gate input IN; when transistor T1 is on, the P-channel output buffer TPO1 is controlled, and when the transistor T2 is on, the N-channel output buffer TNOI is controlled.

FIG. 6 is also a modification of FIG. 2, in which the gate and pre-buffer sections 61 to G3 are used, and the Riki Motoyama buffer circuit is a tri-state circuit. That is, depending on the combination of inputs IN and EN, the output buffer transistors TP01 and TNol are
In addition to the on-off operation relationship, the outputs of the gates G2 and G3 enable the TPOI and TNOI to be turned off at the same time, that is, the output 42 can be placed in a high impedance state.

7 and 8 show an embodiment of the present invention as a one-channel output buffer, in which the output buffer is configured by a P-channel transistor in FIG. 7 and an N-channel transistor in FIG. 8.

That is, in FIG. 7, among the transistors TN11 to TN13 and TPII to TP13 for connecting the divided gates, and in FIG. The through current (
The current between the power supplies via the transistor TPOI or TNOI can be made small, and the same effects as in the previous embodiment can be obtained.

It should be noted that the present invention is not limited to the circuits illustrated in these embodiments, and various other modifications are possible.

[Effects of the Invention] As described above, according to the present invention, by dividing the transistor gate of the output buffer and connecting the gates with a resistor element, the transistor can be turned on gradually. The load capacity can be charged and discharged slowly. Furthermore, by configuring the resistance element with a transistor set to a predetermined size, it is possible to reduce the through current generated during output buffer switching.

As described above, according to the present invention, as the speed of semiconductor devices increases, overshoot and undershoot phenomena that occur in conventional output buffers during output buffer switching can be suppressed, and the penetration between VDD and GND during output buffer switching can be suppressed. Since current can be prevented, malfunctions and latch-up phenomena of other elements sharing the power source can be prevented. Further, according to the present invention, since the total output buffer size remains the same as in the conventional case, it is possible to obtain output current characteristics equivalent to those in the conventional case.

Further, even if the resistance of the gate electrode is reduced, no problem will occur because a resistive element is separately connected to the divided gate, and the signal delay time can be made more accurate.

[Brief explanation of the drawing]

1 to 8 are circuit diagrams of each embodiment of the present invention, and FIG. 9 is a circuit diagram of each embodiment of the present invention.
FIG. 10 is a diagram of a conventional output buffer circuit, FIG. 10 is an input/output characteristic diagram thereof, and FIGS. 11 and 12 are circuit diagrams that further embody FIG. 9. TPOI: P-channel transistor of output buffer, TNOl: N-channel transistor of output buffer, PGII-PG14: P-channel side division gate, NGII-N013: N-channel and 1-channel division gate, S...・Source, D...Drain, DFO1~DF
O3, DFll, DF12...resistance element, TN11~
TN15, TP11 to TP15...transistor for resistance element, IVIO...CMOS inverter. Figure 1

Claims (8)

[Claims] (1) Each gate of a P-channel MOS transistor and an N-channel MOS transistor whose outputs are commonly connected is divided into multiple parts, and the divided P-channel MOS
Connecting the gates of the S transistors with a first resistance element,
An output buffer circuit characterized in that the gates of the N-channel MOS transistors are connected by a second resistance element. (2) The output buffer circuit according to claim 1, wherein diffusion layers are used as the first and second resistance elements. (3) The output buffer circuit according to claim 1, wherein first and second delay circuits constituted by MOS transistors are used as the first and second resistance elements. (4) The first and second delay circuits used as the resistance elements are P-channel MOS transistors whose input sides and output sides are respectively commonly connected and whose gates are given a low-level potential, and whose gates are given a high-level potential. N channel M
OS transistors are used, the gm of the P-channel MOS transistor of the first delay circuit is larger than the gm of the P-channel MOS transistor of the second delay circuit, and the gm of the N-channel MOS transistor of the second delay circuit is larger than the first delay. 4. The output buffer circuit according to claim 3, wherein the gm is larger than the gm of an N-channel MOS transistor in the circuit. (5) A P-channel MO whose input side and output side are commonly connected to the first and second delay circuits used as the resistance elements.
Using an S transistor and an N channel MOS transistor, the gate of the P channel MOS transistor of the first delay circuit is given an input signal of the output buffer and an inverted input, and a high level potential is applied to the gate of the N channel MOS transistor. A low level potential is applied to the gate of the P-channel MOS transistor of the second delay circuit, and an input signal and an inverted input of the output buffer are applied to the gate of the N-channel MOS transistor. g of the P-channel MOS transistor of the first delay circuit
m is larger than gm of the P-channel MOS transistor of the second delay circuit, and gm of the N-channel MOS transistor of the second delay circuit is larger than the gm of the N-channel MOS transistor of the first delay circuit.
Claim 3 characterized in that it is larger than the gm of the transistor.
The output buffer circuit described in . (6) The first delay circuit used as the resistance element is an N-channel MOS transistor whose gate is given a high-level potential, and the second delay circuit is a P-channel MOS transistor whose gate is given a low-level potential. A second delay circuit using a transistor, the input of the output buffer is connected to the source side of each divided gate of the P-channel MOS transistor of the output buffer, and the input of the output buffer and an inverted signal are applied to the gate. The drain side of a P-channel MOS transistor whose gm is larger than that of the channel MOS transistor is connected, and the input of the output buffer is connected to the source side of each divided gate of the N-channel MOS transistor of the output buffer, and the input of the output buffer is connected to the gate. An N-channel MOS whose gm is larger than that of the N-channel MOS transistor of the first delay circuit to which an inverted signal is applied.
4. The output buffer circuit according to claim 3, wherein the drain side of the transistor is connected. (7) A claim characterized in that the N-channel side circuit of the output buffer connected between the divided gates by a resistor element is removed, and the transistor having the divided gate is configured only with the P-channel side output buffer. The output buffer circuit according to any one of items 1 to 6. (8) A claim characterized in that the P-channel side circuit of the output buffer connected between the divided gates by a resistive element is removed, and the transistor having the divided gate is configured only with the N-channel side output buffer. The output buffer circuit according to any one of items 1 to 6.