JPS6284362A - Microprocessor - Google Patents

Abstract

PURPOSE:To share an input terminal by detecting the time width of a reset signal and a synchronizing signal between chips so as to input the reset signal and the synchronizing signal to the same input terminal. CONSTITUTION:An input signal B having a period being one period or over and <3 periods of a reference clock A is synchronized with the reference clock by a flip-flop (FF) 3 and becomes a signal C. Further, the signal is delayed by flip-flops 4a, 4b and a reset (R) signal F is obtained to the inside of D. Since the synchronizing signal E is an output of AND between the signals C, D, no change is caused. The reset signal D and the synchronizing signal E are generated from the input signal B whose time width is >=3 periods of that of the reference clock A.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a microprocessor, and relates to a microprocessor and a microprocessor, which is an l-chip capable of inputting an external reset signal and an inter-chip synchronization signal to the same input terminal. It concerns microprocessors.

(Prior Art) Generally, in a system that uses a microprocessor to perform complex processing, a system configuration is adopted in which several microprocessors are made to work together, or a microprocessor and other peripheral LSI are made to work together. Here, in order for multiphase clock type microprocessors that require multiple clock cycles to execute one instruction to exchange signals, it is necessary to make the instruction execution timing of each microprocessor the same. There is.

Conventional microprocessors have a synchronization signal input terminal, and each microprocessor can be synchronized by synchronization signals sent from a master processor, or multiphase clocks can be input from separate terminals. death,
It was designed to synchronize each microprocessor.

By the way, the progress of LSI technology in recent years has been remarkable.
The degree of integration of chip microprocessors has been increasing year by year, their functions have been improved, and the number of external input/output signals has been increasing. However, since the number of terminals that can be extracted is determined by the peripheral length of the chip, there is a natural limit to increasing the number of terminals, and L
How to reduce the number of SI terminals is an important issue in LSI design.

(Problems to be Solved by the Invention) However, in the microprocessor having the above configuration, since input terminals for signals for synchronizing the microprocessors are provided independently, there is a problem in that the number of terminals increases. . Furthermore, as the number of terminals increases, the chip area increases, leading to an increase in cost.

The present invention solves the above-mentioned problems and provides a microprocessor in which input terminals for a reset signal and a synchronization signal between processors are shared.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a plurality of terminals,
In a microprocessor equipped with an internal circuit including a circuit that performs arithmetic operations and signal processing based on input signals from these terminals, signals input to one of the plurality of terminals and set to different predetermined time widths are used. A signal detecting means is provided for detecting a plurality of input signals based on the size of the time width and outputting the detected signals to necessary parts of the internal circuit.

Preferably, the signal detection means includes a flip-flop synchronized with a reference clock and N stages (N
is an integer greater than or equal to 1), and a dart that performs the logical product of the input signal of the first stage and the output signal of the final stage of the flip-flop.

(Operation) According to the present invention, since the microprocessor is configured as described above, the technical means operates as follows. The signal detection means detects a plurality of input signals inputted to one terminal, such as a reset signal and an inter-chip synchronization signal, based on the size of each time width (Cruz width), and detects the internal circuit. Works to supply the necessary parts. Therefore, the input terminals that were provided separately for the reset signal and the synchronization signal can be shared and used as one terminal, so that the problems of the prior art described above can be solved.

(Example) The present invention will be described in detail with reference to FIGS. 1 to 6.

FIG. 1 is a block diagram showing the main parts of an embodiment of the microprocessor of the present invention, showing the input terminal of the microprocessor, the internal parts of the normal arithmetic and signal processing circuit, the polyphase tarlock generation circuit, etc. described later. FIG. 3 is a block diagram of a signal detection circuit provided between the circuit. In the figure, ■ is an input terminal for inputting a reset signal (RES) and a synchronization signal (SYN), 2 is an input terminal for inputting a reference clock, and 3 is a reference clock.

Flip-frog for synchronization, 4 a t4
b is a delay flip-flop that delays the signal from flip-flop 7o horn 3, 5 is an AND dart that takes the AND of the output of flip-flop 3 and the output of flip-flop 4b (point B), and 6 and 7 are resets, respectively. This is a signal line that supplies signals and synchronization signals to internal circuits.

A reset signal or a synchronization signal is inputted to the input terminal 1 from the outside, and a reference clock signal is inputted to the input terminal 2. A reset or synchronization signal is synchronized to the reference clock by the flip-flop 3, and this signal is further delayed by the flip-flops 4a, 4b.

This output signal from the Pflozzo 4b is supplied to necessary portions within the LSI via the signal line 6 as a reset signal to the internal circuits. Further, the AND gate 5 takes the AND of the input signal of the delay flip-flop 4a and the output signal of the delay flip-flop 4b, and the output signal is sent to the multiphase clock generation circuit (described later) via the signal line 7. Serves as a synchronization signal.

Next, the operation of the above signal detection circuit is shown in FIGS. 2(a) and 2(b).
) will be explained according to the time chart. Here, (a)
is the reference clock given externally, (b) is the signal manually input from input terminal 1 in Figure 1, r is the signal at point A in Figure 1, and (b) is the signal at point B in Figure 1. The reset signal to the internal circuit, (e) is the output signal of the AND gate 5, and the synchronization signal is shown.

Figure 2 (,
). The input signal (b) is synchronized with the reference clock by the flip-flop 3, and becomes the signal (c). Furthermore, it is delayed by flip-flops 4a and 4b, and a reset signal to the inside of 2) is obtained. The synchronization signal (e) is (c)toni)
Since this is the output of the AND of the signals, no change occurs here.

Figure 2(b) shows a case where the time width of the input signal to input terminal 1 is three cycles or more of the reference clock; in this case, it is used as a reset signal to the internal circuit) and a synchronization signal Both signals (e) are generated. In other words, the input signal (b)
If the time width is less than three cycles of the reference clock, this signal is regarded as a reset signal, and if it has a time width of three cycles or more, it is regarded as a synchronization signal.

Here, when the number of delay flip-flops shown in FIG. 1 4a and 4b is N (N=1, 2, 3, etc.), the signal applied to input terminal 1 should be used as a reset signal. For example, the time width Tr of the applied signal may be set as follows.

If the signal applied to the input terminal 1 is to be a synchronization signal, the time width Ti of the applied signal may be set as follows.

Tf≧(N+i)xτ As long as the above condition is satisfied, it is possible to set a reset signal and a synchronization signal to the internal circuit with an arbitrary time width.

As shown in Table 1, when a reset signal is given as an input signal, the output of the signal detection circuit is only a reset signal to the internal circuit, but when a synchronization signal is given as an input signal, In addition to the synchronization signal (7) to the internal circuit (multiphase clock generation circuit), a reset signal (62) to the internal circuit is also generated, but this does not pose any practical problem.

Next, a multiphase tarlock generation circuit that generates a multiphase clock using a synchronization signal detected by a signal detection circuit will be explained using a two-phase clock generation circuit as an example.

FIG. 3 is a circuit diagram showing an example of a two-phase clock generating circuit, and FIG. 4 is a time chart showing its operation. As shown in FIG. 3, the two-phase clock generation circuit includes a flip-flop 10, inverters 11 and 12, and AND gates 13 and
Consists of 4.

While the synchronization signal input to the reset terminal of the flip-flop 10 via the inverter 11 is generated (°'
H” level) is the output of flip-flop 10 (point D)
becomes "L" level, and neither a one-phase clock (φ1) nor a two-phase clock (φ2) occurs in the outputs of the AND darts 13 and 14. When the synchronization signal goes to "L" level, a signal that turns on/off at the rising edge of the reference clock is obtained at point D, so the output of 13.14 has φ1. A clock of φ2 is generated. This timing is uniquely determined only by the reference clock and synchronization signal, so by giving the same reference clock and synchronization signal to multiple microprocessors, the instruction execution timing of multiple microprocessors can be matched. can be done. Finally, it becomes possible to operate a system consisting of multiple microprocessors in a unified manner.

FIG. 5 is a circuit diagram showing a modification of the signal detection circuit shown in FIG. 1;
FIG. 6 is a time chart showing the operation. In FIG. 5, the same reference numerals as in FIG. 1 indicate the same components. The difference from the one in FIG. 5 is the part from which the reset signal is taken out. That is, the reset signal is obtained by calculating the logical sum of the outputs (points A, C, and B) of the seven lip-flops 3.4a and 4b using the logical sum r-)8.

As shown in the time chart of FIG. 6, the length of the reset signal () can be made longer, making it easier to reset each part within the microprocessor.

(Effects of the Invention) As explained above, according to the present invention, by providing a signal detection means for detecting whether the input signal is a reset signal or a synchronization signal, depending on the time width of the input signal, Input terminals can be shared. In highly integrated LSIs such as one-chip microprocessors, the number of terminals tends to be large relative to the chip area, and reducing the number of terminals is an important issue. That is,
The number of terminals that can be taken out depends on the peripheral length, so if the number of terminals is reduced by even one bin, the extra chip area required to secure the number of terminals is reduced, and the number of chips that can be taken out from one wafer is increased. We can expect lower prices. Furthermore, if there is a surplus in the number of terminals, it can be expected that by allocating other input/output signals to the reduced number of bins, the functionality will be improved accordingly.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the main parts of a microprocessor showing an embodiment of the present invention, Fig. 2 (,) (b) is a time chart showing the operation of the embodiment of Fig. 1, and Fig. 3 is a two-phase A circuit diagram showing one row of lock generation circuits, Figure 4 is similar to 2 in Figure 3.
Time chart showing the operation of the phase lock generation circuit, No. 5
This figure is a block diagram showing a modification of the embodiment shown in FIG. 1, and FIG. 6 is a time chart showing the operation of the modification of FIG. 5. 1, 2...input terminal, 3, 4 a, 4 b
, 10 =-flipflop, 5.13.14・
...Logical product dart, 6.7...Signal line, 8...Logical sum date, 11.12...Inverter. Patent Applicant Oki Electric Industry Co., Ltd. Patent Application Agent Patent Attorney Megumi Yamamoto - Figure 1 (Q) (b) No. 11, 9al'pld＼RINOMU~-Hi Figure 2 2 Interest Guro Sogui So β Migration Figure 3 $3 Z qttyl'F4Ab'rv-To Figure 4

Claims (2)

[Claims] (1) In a microprocessor equipped with a plurality of terminals and an internal circuit including a circuit that performs arithmetic operations and signal processing based on input signals from these terminals, a signal input to one terminal among the plurality of terminals is used. A microprocessor comprising signal detection means for detecting a plurality of input signals set to different predetermined time widths based on the magnitude of the time width and outputting the detected signals to necessary parts of the internal circuit. (2) The signal detecting means includes a flip-flop synchronized with the reference clock, an N-stage flip-flop (N is an integer of 1 or more) that delays the output, and an input signal at the first stage of the flip-flop and an input signal at the final stage of the flip-flop. 2. The microprocessor according to claim 1, further comprising a gate that performs an AND operation with an output signal.