JPS6284533A - Manufacture of semiconductor large-scale integrated circuit - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor large-scale integrated circuit efficiently by forming a power supply line common in cells, connecting and disconnecting one cell and the power supply line and testing all cells in succession. CONSTITUTION:Power supply lines L1, L2 for a test are connected to cells (a)-(f). A branch line Ls consists of Lsm connected to the power supply line and Lsc connected to the cell, and is brought to the state in which Lsm and Lsc are cut off by a node t1 before the test. The node t1 is irradiated by a laser before the test, and an amorphous silicon film 3 and a molybdenum film 4 are heated, thus forming a molybdenum silicide film 5. Consequently, the branch lines Lsm and Lsc are connected electrically. Electricity is supplied from the power supply lines, and the test is conducted. The branch line Lsm consisting of aluminum is melted and cut through laser exposure. Accordingly, the cells (b), (c), (d) for a large-scale integrated circuit are tested, thus discriminating all defective or nondefective cells.

Description

[Detailed Description of the Invention] [Summary] In a test in which a wafer-scale IC consisting of a plurality of cells (or cell blocks) is tested in wafer form, a common power supply line is provided to the cells, and the power supply line and the cells are connected in advance. Keep it electrically disconnected and connect it to 1 before testing.
The test is performed by connecting one cell to the power line, and after the test, the power line is disconnected again, thus sequentially testing all the cells one by one.

To make this connection, for example, a laminated part of an amorphous silicon layer and a metal layer is irradiated with a laser to create a silicide layer (conductive layer).
To form and separate the power line, any position on the power line is irradiated with a laser to melt and separate.

[Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor large-scale integrated circuit, and more particularly, to a method for manufacturing a large-scale integrated circuit using a semiconductor wafer as a substrate.

ICs have made remarkable progress with LSI and VLSI, becoming more highly integrated and densely packed. This is because the more highly integrated and densely packed there is, the more performance there is, such as high-speed operation.

However, even if the integration is advanced to a high degree, if it does not lead to a high yield, it will not be widely used as an IC, and the manufacturing method must be sufficiently considered to achieve a high yield.

[Problems to be Solved by the Prior Art and the Invention] Cells of the same type or of multiple types (hereinafter, for the purpose of explanation, cells or cell blocks consisting of ICs are collectively referred to as cells) are placed on a 34-inch diameter or 6-inch diameter wafer. The so-called wafer-scale IC (wafer scale IC) has been devised. This wafer scale IC is the most two-dimensionally highly integrated IC.

One of the most important issues in such two-dimensional wafer scale ICs is the testing method.

Since the wafer process consists of many fine and complicated steps, the probability that all of the cells on the wafer that have completed the wafer process and cell elements will be good is low, and in particular, the causes of defects are Most of the problems are caused by the power source. Therefore, if you test a large number of cells on a wafer with a common power line, all the cells with the common power line will become defective due to power failure, and the yield of wafer-scale ICs will be extremely low, resulting in poor product quality. Selling it would be unreasonably high cost.

For this reason, a manufacturing method has been adopted in which only non-defective products are selected and only non-defective products are wired and connected, but this has other problems, and currently no manufacturing method that includes a fully satisfactory testing method has been obtained.

One of the conventionally known test methods is to provide a pad for externally supplying power to each of a large number of cells, and to contact the pad with a probe (needle) to test the large number of cells on a wafer. This is a so-called probe test method, in which each test is performed one by one. However, this test method
All cells must be banded. and,
Since the probe is brought into contact with the pad, if a cell element is provided under it, that cell element will be destroyed.

Therefore, the pad area is provided separately, and the band area has the disadvantage that high integration of the wafer is hindered.

Another test method is to provide a power line for each cell instead of a pad and supply power from the terminal without using a probe, but this also impairs the degree of integration, as mentioned above. This method is no different from the probe test method, and in fact, it is a method that further deteriorates the degree of integration.

The present invention proposes a manufacturing method including testing of wafer scale ICs that eliminates these problems.

[Means to solve the problem] The purpose is to create multiple cells (cells or cell blocks)
When testing a wafer-scale semiconductor integrated circuit in wafer state, a common power supply line is provided to the cells,
After the power supply line and the cell are electrically disconnected in advance, one cell is connected to the power supply line for testing, and after the test, the power supply line is disconnected again. This is achieved by a method of manufacturing semiconductor large-scale integrated circuits in which everything is tested.

To connect the cell and power line before the test, for example, irradiate the laminated part of the amorphous silicon layer and metal layer with a laser to form a silicide layer, and to disconnect the power line after the test, A method of melting and separating by irradiating a laser beam on an arbitrary position is used.

[In other words, in the present invention, a common power line is provided to all cells in advance, the power line is separated from the cells, and one cell is connected to the power line before testing. After testing, the power line is again disconnected, thus testing all of the cells one by one in sequence.

Then, the cells can be tested individually and the power line area can be used as an area for actual wiring on a wafer scale C, so that the degree of integration can be increased without hindering the degree of integration.

[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.

FIG. 1 shows a schematic plan view of a wafer-scale IC according to the present invention, showing power supply lines Ll+L2 for partial testing on one wafer surface and a plurality of cells a to be connected thereto.
~f is illustrated. Power line L1 is Vdd line,
The power supply line L2 is a Vss line, and pads p, , p2 are connected to them, and a terminal or a probe is brought into contact with this band to supply power. In addition, these power supply lines and pads are both made of an aluminum film, and the power supply line has a film thickness of 0.5 to 1 μm and a width of 50 to 1 μm, for example.
The wiring is about 00 μm. Furthermore, as shown in the figure, the power supply line L1. A branch line Ls is provided from L2 and can be connected to each of cells a to r.

In this example, two power supply lines L, L2 are provided, but if one of the lines is a ground line connected to the wafer substrate, only one power supply line may be used.

FIG. 2 is an enlarged partial plan view of one branch line Ls, where the branch line Ls consists of Lsm connected to a power supply line and Lsc connected to a cell, and such a power supply connection branch line Lsm and a cell connection branch line Before the test, Lsc is disconnected at the connection point t1 and is in an electrically isolated state. When testing the branch line in this state, Lsm and Lsc of only one cell are electrically connected.

Figures 3(a) and Cb) are cross-sectional views showing the connection method.
FIG. 3 is a sectional view of a portion of the connection point t1 in FIG. 2; In the figure,
Figure 3(a) shows the electrically disconnected state; 1 is the wafer substrate, 2.2' is the insulating film, 3 is the amorphous silicon film, 4 is the molybdenum film, and other symbols are the same as in Figure 2. The parts are marked with the same symbols. At this time, the amorphous silicon film (thickness: 1000 to 2000) is pure silicon without any impurities, so it is an insulator, so the power supply connection branch lines L, sm and the cell connection branch line Lsc are separated. and are electrically isolated. Moreover, the molybdenum film 4 is not limited to molybdenum, and may be other metal films such as a titanium film.

Then, when testing is to be carried out, this part is irradiated with a laser, and as shown in FIG. 3(b), the amorphous silicon film 3 and the molybdenum film 4 are heated and reacted to form a molybdenum silicide film 5. .

This irradiation is a narrowly focused laser beam, and a helium-neon laser is used as the light source. Then, since the molybdenum silicide film is a conductor, the power supply connection branch line LslT+ and the cell connection branch line Lsc are electrically connected, and power can be supplied to the cell a.

Then, by using a signal line (not shown),
A test is performed by supplying power from the above power supply line to determine whether cell a is good or bad.

Thus, after the test is completed, the power supply connection branch line Lsm connected to the power supply line L is disconnected. This is done at the cutting point t2 shown in FIG. 2, as shown in FIG. 4(a).

The cutting method is shown in the cross-sectional view ('b). The same figure (a
) is in the electrically connected state, and the symbol in the figure is the third
The same symbols as in the figure are attached. The same figure (bl shows the state in which the branch line Lsm made of aluminum is melted and cut by laser irradiation.The laser irradiation for cutting is performed using a high-power laser for a short period of time, compared to the irradiation for connection described above. A method of time irradiation is used.

In this way, cells b, c, and d are sequentially tested to determine whether all cells are good or bad. Once all the cells on the wafer have been identified, actual wiring is performed based on the information G. A method is used in which the actual wiring is formed on the test power supply line with an insulating film interposed therebetween. Of course, the test power supply line may be removed and the actual wiring may be provided thereafter.

The connection and disconnection of the power supply line described above is automatically performed in real time under computer control in combination with cell testing.

Also, whether to form the power supply line for the above test into multiple power lines connecting several cells on the wafer or a single power line connecting all the cells on the wafer depends on the integration density. It is desirable to have a method that takes this into account and makes decisions in conjunction with cell design.

In addition, although cells have been described above as test units, a plurality of cells (cell blocks) may be used as test units in consideration of wafer process yield.

[Effects of the Invention] As is clear from the above description, the present invention has a great effect in that wafer scale ICs can be highly integrated and efficiently manufactured.

[Brief explanation of drawings]

FIG. 1 is a schematic plan view of a wafer scale IC according to the present invention, FIG. 2 is an enlarged plan view of a branch line portion of the power supply line, and FIGS. 3(a) and 3(b) are sectional views showing a connection method. 4(al) and (b) are cross-sectional views showing the cutting method. In the figures, 1 is a wafer, 2.2' is a green edge film, 3 is an amorphous silicon film, 4 is a molybdenum film, and 5 is molybdenum silicide. membrane, a to f are cells, L l + L 2 are power lines, PI + P 2 are pads connected to the power lines,
Ls, Lsm, and Lsc are branch lines of the power supply line, tl is a connection point, and t2 is a disconnection point. 4 people, 58 months, t=v-?) Sea urchin - Thru IC's 1000th motion sound 1z Fig. 1 4r sound sound p 5 minutes - Otomo plane 1st edition 2nd fig. 3 @4 flash

Claims (2)

[Claims] (1) When testing a wafer-scale semiconductor integrated circuit consisting of a plurality of cells or a plurality of cell blocks in a wafer state, a common power supply line is provided to the cells or cell blocks, and the power supply line and the cell or cell block are tested. 1 before testing.
A semiconductor large-scale integrated circuit characterized in that a test is performed by connecting one cell or cell block to a power line, and after the test, the power line is disconnected again, so that all of the cells or cell blocks are sequentially tested. manufacturing method. (2) To connect one of the cells or cell blocks to the power supply line before the test, a silicide layer is formed by irradiating the laminated part of the amorphous silicon layer and the metal layer with a laser;
2. The method of manufacturing a semiconductor large-scale integrated circuit according to claim 1, wherein the power supply line is disconnected after the test by irradiating a laser at an arbitrary position on the power supply line to melt and separate the power supply line.