JPS6284836U - - Google Patents
Info
- Publication number
- JPS6284836U JPS6284836U JP17457885U JP17457885U JPS6284836U JP S6284836 U JPS6284836 U JP S6284836U JP 17457885 U JP17457885 U JP 17457885U JP 17457885 U JP17457885 U JP 17457885U JP S6284836 U JPS6284836 U JP S6284836U
- Authority
- JP
- Japan
- Prior art keywords
- address
- read
- write
- count output
- random access
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
Description
第１図は本考案の非同期データ書き込み読み出
し回路の構成を示す図、第２図は同、ランダムア
クセスメモリの書き込み、読み出し動作が実行さ
れるアドレスを示す図、第３図は同、入力データ
の書き込み、読み出し動作とその出力との関係を
示す図、第４図は従来の非同期データ書き込み読
み出し回路の構成を示す図である。
１……書き込み用アドレスカウンタ、２……読
み出し用アドレスカウンタ、３……アドレスセレ
クタ、４……ランダムアクセスメモリ、５……入
力バツフア回路、６……ラツチ回路、７……反転
手段、８……インバータ回路。
FIG. 1 is a diagram showing the configuration of the asynchronous data write/read circuit of the present invention, FIG. 2 is a diagram showing the addresses at which write and read operations of the random access memory are executed, and FIG. FIG. 4 is a diagram showing the relationship between write and read operations and their outputs, and is a diagram showing the configuration of a conventional asynchronous data write and read circuit. DESCRIPTION OF SYMBOLS 1... Address counter for writing, 2... Address counter for reading, 3... Address selector, 4... Random access memory, 5... Input buffer circuit, 6... Latch circuit, 7... Inverting means, 8... ...Inverter circuit.
Claims (1)
して、 〔Ｗｎ Ｗｎ―１…Ｗｉ…Ｗ２ Ｗ１〕 なるカウント出力を出力する書き込み用アドレ
スカウンタ１。 (ロ) 読み出しアドレスクロツクＲａをカウント
して、 〔Ｒｎ Ｒｎ―１…Ｒｉ…Ｒ２ Ｒ１〕 なるカウント出力を出力する読み出し用アドレ
スカウンタ２。 (ハ) 上記書き込み用アドレスカウンタ１、読み
出し用アドレスカウンタ２のカウント出力を選択
して、当該カウント出力によりランダムアクセス
メモリ４の書き込み、読み出しが実行されるアド
レス 〔Ｗｎ Ｗｎ―１…Ｗｉ…Ｗ２ Ｗ１〕 または 〔Ｒｎ Ｒｎ―１…Ｒｉ…Ｒ２ Ｒ１〕 をセレクトするアドレスセレクタ３。 (ニ) ランダムアクセスメモリ４。 からなり、入力データを上記書き込みアドレスク
ロツクＷａに同期して形成された書き込み信号Ｗ
ｒに同期して上記ランダムアクセスメモリ４の指
定のアドレスに逐次書き込み、指定のアドレスに
書き込まれた入力データを上記読み出しアドレス
クロツクＲａに同期して形成されたラツチ信号Ｒ
ｒに同期して逐状読み出すように構成において、 (ホ) 上記書き込み用アドレスカウンタ１のカウ
ント出力 〔Ｗｎ Ｗｎ―１…Ｗｉ…Ｗ２ Ｗ１〕 の所定の桁のビツト出力〔Ｗｉ〕を反転して、 〔Ｗｎ Ｗｎ―１……Ｗ２ Ｗ１〕 なる出力を得る反転手段７。 を具備し、当該反転手段７の出力 〔Ｗｎ Ｗｎ―１……Ｗ２ Ｗ１〕 によつて指定されるランダムアクセスメモリ４の
アドレスから入力データを逐次書き込むとともに
、上記読み出し用アドレスカウンタ２のカウント
出力 〔Ｒｎ Ｒｎ―１…Ｒｉ…Ｒ２ Ｒ１〕 によつて指定されるランダムアクセスメモリ４の
アドレスから入力データを逐次読み出すことを特
徴とする非同期データ書き込み読み出し回路。[Claims for Utility Model Registration] (a) A write address counter 1 that counts the write address clock Wa and outputs a count output of [Wn Wn-1...Wi...W2 W1]. (b) A read address counter 2 that counts the read address clock Ra and outputs a count output of [Rn Rn-1...Ri...R2 R1]. (c) Select the count output of the write address counter 1 and the read address counter 2, and select the address at which writing and reading from the random access memory 4 is performed according to the count output [Wn Wn-1...Wi...W2 W1 ] or [Rn Rn-1...Ri...R2 R1] Address selector 3 that selects. (d) Random access memory 4. A write signal W is formed by synchronizing the input data with the write address clock Wa.
The input data written to the specified address is read out by a latch signal R formed in synchronization with the read address clock Ra.
(e) Invert the bit output [Wi] of a predetermined digit of the count output [Wn Wn-1...Wi...W2 W1] of the write address counter 1 in synchronization with r. , [Wn Wn-1...W2 W1]. The input data is sequentially written from the address of the random access memory 4 specified by the output of the inverting means 7 [Wn Wn-1...W2 W1], and the count output of the read address counter 2 [ Rn Rn-1...Ri...R2 R1] An asynchronous data write/read circuit characterized in that input data is sequentially read from an address of a random access memory 4 specified by RnRn-1...Ri...R2R1].
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17457885U JPH0241693Y2 (en) | 1985-11-13 | 1985-11-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17457885U JPH0241693Y2 (en) | 1985-11-13 | 1985-11-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6284836U true JPS6284836U (en) | 1987-05-30 |
| JPH0241693Y2 JPH0241693Y2 (en) | 1990-11-07 |
Family
ID=31113092
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17457885U Expired JPH0241693Y2 (en) | 1985-11-13 | 1985-11-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0241693Y2 (en) |
-
1985
- 1985-11-13 JP JP17457885U patent/JPH0241693Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0241693Y2 (en) | 1990-11-07 |
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