JPS6433242U

JPS6433242U -

Info

Publication number: JPS6433242U
Application number: JP12815987U
Authority: JP
Priority date: 1987-08-24
Filing date: 1987-08-24
Publication date: 1989-03-01

Description

[Brief explanation of the drawing]

第１図は本考案の構成図、第２図はＲＡＭ１の
構成図、第３図は本考案の実施例のブロツク図、
第４図は第３図のタイムチヤート、第５図はＲＡ
Ｍ１５の構成例を示す図、第６図は従来例のブロ
ツク図、第７図は従来例のタイムチヤート及び、
第８図はＲＡＭ６１−１〜６１−Ｐの構成例を示
す図である。図に於いて、１，１５，６１−１〜６１−Ｐ…
…ＲＡＭ、２……ラツチ手段、３，１２，６２…
…コード検出回路、４……書込読出手段、５，１
７，６５……保護回路、１３……セレクタ、１４
，６３……スリーステートバツフア、１６，６４
……ラツチバツフア、１８……フリツプフロツプ
。 FIG. 1 is a block diagram of the present invention, FIG. 2 is a block diagram of RAM 1, and FIG. 3 is a block diagram of an embodiment of the present invention.
Figure 4 is the time chart of Figure 3, Figure 5 is the RA
A diagram showing an example of the configuration of M15, FIG. 6 is a block diagram of the conventional example, and FIG. 7 is a time chart of the conventional example, and
FIG. 8 is a diagram showing an example of the configuration of the RAMs 61-1 to 61-P. In the figure, 1, 15, 61-1 to 61-P...
...RAM, 2...Latch means, 3, 12, 62...
...Code detection circuit, 4...Writing/reading means, 5, 1
7, 65...protection circuit, 13...selector, 14
,63...Three-state buffer, 16,64
...Flip Flop, 18...Flip Flop.

Claims

[Claims for Utility Model Registration] In a code detection and protection circuit where the number of protection stages is α and the number of channels of input time-division multiplexed signals is β, the code detection protection circuit has a storage capacity of α×β bits or more, and A RAM having an N-bit configuration in which a plurality of addresses are assigned to each of the time-division multiplexed channels, a latch means for latching the N-bit-configured data read from the RAM, and the time-division multiplexed A code detection circuit outputs a code detection result indicating whether or not the code accommodated in each channel of the signal is a predetermined code; and the code detection circuit outputs a code detection result of a specific channel. When the contents of a plurality of addresses assigned to the specific channel of the RAM are sequentially read from the youngest address and latched by the latch means, and the contents of the youngest address are latched by the latch means, The code detection result of the specific channel output from the code detection circuit is written to the least significant bit of the youngest address, and the data latched by the latch means is shifted bit by bit to the most significant bit. When writing to a younger address and causing the latch means to latch the contents of an address other than the youngest address, the data latched by the latch means is shifted bit by bit to the most significant bit side and written to the original address. write/read means for writing the data stored in the most significant bit of the previous address into the least significant bit of the original address; 1. A code detection protection circuit comprising: a protection circuit for determining whether or not a code has been established.