JPS6285364A - Bus control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a bus control system, particularly a bus control system in which the right to use a bus shared by a plurality of units is granted by determining permission to use a bus in response to a request from a unit. Related to timeout error handling in bus control systems.

(Prior art) When a unit that has obtained permission to use the bus is performing an operation using the bus such as data transfer (hereinafter referred to as bus operation), a failure occurs that prevents the unit from completing the bus operation. This may occur. For example, there is a failure in which permission to use the bus is issued to a unit that has not made a request to use the bus, or a failure in which the unit continues to have permission to use the bus even though it has been granted permission to use the bus.

When such a failure occurs, other units are unable to use the bus, and although originally it would have been sufficient to stop the bus operation of only the unit concerned, the bus operation of all units becomes disabled.

In order to eliminate such problems, conventional bus control methods detect a timeout error when a bus operation is not completed within a predetermined time, and report this timeout error signal to a higher-level device. , the system waits for a recovery operation from the host device.

(Problems to be Solved by the Invention) In such conventional systems, the recovery operation in the host device is performed by, for example, a microprogram, so it takes a long time compared to bus operations such as data transfer. In short, the first problem is that essentially the entire bus system goes down temporarily, and it is not just an internal failure of a specific unit, but a circuit that determines permission to use the bus. A second problem is that it is difficult for the host device to recover from failures due to disconnection of the bus use request input line to the circuit or short circuit of the bus use permission output line from the same circuit.

(Means for Solving the Problem) The system of the present invention is a bus control system in which the right to use a bus shared by a plurality of units is granted by determining permission to use the bus in response to a request from a unit. a timeout detection means for detecting a timeout error when a bus operation by a unit that has acquired the right has not been completed within a predetermined time; and a bus user identification device for identifying the unit that requested the bus operation that caused the timeout error. a bus forced release means for relinquishing the right to use the bus and releasing the bus when a time-out error is detected; It is assumed that a bus request ignoring means is provided to ignore a bus use request from a request source unit for a bus operation that is currently being performed.

(Example) Next, embodiments of the present invention will be described with reference to the drawings.

1 and 2 are block diagrams showing one embodiment of the present invention.

First, referring to FIG. 2 showing the overall picture of this embodiment, this embodiment has bus forced release circuits Fl, F2 . F
3...N units having FN and sharing bus BUS) Ul, U2. It consists of U3...UN and a bus control unit BCU whose details are shown in FIG.

When attempting to perform an operation (bus operation) that uses the bus BUS, such as data transfer, each of Ul to UN asynchronously sends a bus usage request X (X = x to N).
is output to the bus control unit (BCU). In response to these bus use requests RX, the bus control unit BCU grants bus use permission AY (Y-1 to
N) to respond. Only the unit UY that has received permission to use the bus AY is allowed to use the bus BUS and performs bus operations. Bus control unit BCU
monitors the read signal line, write signal line, etc. in the bus BtJS to detect the start and end of the bus operation, and is used to start and stop timing, respectively, which will be described later.

Next, referring to FIG. 1 showing details of the bus control unit ECU, this bus control unit ECU includes a bus request ignore circuit RNG, a bus right determination circuit ACK, a bus user retention circuit BUM, and a timeout detection circuit. It has a TED and a bus sequence control circuit B8Q.

During normal operation, bus use request circuits 1 to RN pass through the path request ignore circuit NG and pass to the bus right determination circuit A CK.
The bus right determination circuit ACK outputs one bus use permission AY based on a predetermined priority order. The unit UY that has obtained the bus use permission AY is stored in the bus user holding circuit BUM.

On the other hand, as described above, the path sequence control circuit BSQ monitors a specific signal line in the bus BUS, and when the unit UY starts bus operation, it activates the timeout detection circuit TED to start timing. When it is detected that the bus operation has ended within a predetermined time, the timeout detection circuit TED stops measuring time and clears the time measured up to that point. In this case, the unit UY stored in the bus user holding circuit BUM is of no use.

By the way, if the bus operation does not end within a predetermined time due to the above-mentioned failure, the timeout detection circuit TED outputs the time act error signal TER, to all units Ul to UNK, and also outputs the bus user ignore circuit RN.
Activate G.

All units U to which the timeout error signal TER was input
Among the bus forced release circuits F1 to FN of 1 to UN, the bus forced release circuit FY forcibly terminates the use of the bus BUS by the unit UY. The timeout error signal TER is
It also clears the results monitored by the bus sequence control circuit BSQ.

Bus request ignore circuit RNG activated as described above
stores the unit UY stored at that time in the bus user holding circuit BUM, and if there is a bus use request RY from this unit UY, it will be ignored from now on and output to the bus use right determination circuit ACK. Doesn't work like that. As a result, the unit UY that has generated the time act error is excluded from the determination of permission to use the bus.

(Effects of the Invention) According to the present invention, as explained above, a unit that does not complete its bus operation within a predetermined time is forcibly released from the bus, and the bus is no longer available after that. By providing a means to exclude the bus from being subject to determination of usage permission, it is possible to promptly eliminate the continued unjust monopolization of the bus to a specific unit, and the effect is that the bus can be used more effectively. There is.

[Brief explanation of drawings]

1 and 2 show one embodiment of the invention. RNG: bus request ignoring circuit, ACK: bus usage right determination circuit, BUM: music bus user retention circuit, TED: timeout detection circuit, B8Q:
・−+−+Hasjitance control circuit, Ul, U2. U3
~UN...Unit, Fl, F2. F3~FN
...Bus forced release circuit, ECU...Bus control unit, BUS...Song bus.

Claims (1)

[Scope of Claims] In a bus control system in which the right to use a bus shared by a plurality of units is granted by determining permission to use a bus in response to a request from the unit, the bus operation by the unit that has acquired the right to use is provided. timeout detection means for detecting a timeout error if the bus operation is not completed within a predetermined time; bus user identification holding means for identifying and holding the requesting unit of the bus operation that has generated the timeout error; A bus forced release means that releases the bus by relinquishing the right to use the bus upon detection of a timeout error, and a bus request that ignores the request from the requesting unit when making the determination after the time the bus is released. A bus control method characterized by providing an ignoring means.