JPS628639U - - Google Patents

Info

Publication number
JPS628639U
JPS628639U JP1985099636U JP9963685U JPS628639U JP S628639 U JPS628639 U JP S628639U JP 1985099636 U JP1985099636 U JP 1985099636U JP 9963685 U JP9963685 U JP 9963685U JP S628639 U JPS628639 U JP S628639U
Authority
JP
Japan
Prior art keywords
semiconductor device
lead pin
semiconductor package
groove
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985099636U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985099636U priority Critical patent/JPS628639U/ja
Publication of JPS628639U publication Critical patent/JPS628639U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図ａ，ｂは第１実施例の半導体デバイスの
底面図および要部断面図、第２図ａ，ｂは第２実
施例の半導体デバイスの底面図および要部断面図
、第３図は他の実施例を示す部分底面図、第４図
ａ，ｂは従来の半導体デバイスの底面図および要
部断面図を示す。 ２，１２，２２…半導体パツケージ、４，１４
，２４…リードピン、６…凹部、８…突部、１０
，２０…半導体デバイス、１６，２６…凹溝。

Claims (1)

  1. 【実用新案登録請求の範囲】 １ 半導体パツケージから延出するリードピンを
    該半導体パツケージの裏面内方向に折曲した半導
    体デバイスにおいて、 前記リードピンの折曲部内方向に位置する半導
    体パツケージにリードピンの折曲形状に沿つて突
    部を設けるとともに、前記半導体パツケージのリ
    ードピン先端部分に、リードピン先端を入れるよ
    うに、リードピンの並列方向の凹溝を設けたこと
    を特徴とする半導体デバイス。 ２ 前記凹溝の両端を閉塞したことを特徴とする
    実用新案登録請求の範囲第１項記載の半導体デバ
    イス。 ３ 前記凹溝の両端を開放したことを特徴とする
    実用新案登録請求の範囲第１項記載の半導体デバ
    イス。 ４ 前記凹溝を、複数に区別したリードピン群ご
    とに区画したことを特徴とする実用新案登録請求
    の範囲第１項および第２項記載の半導体デバイス
    。
JP1985099636U 1985-06-28 1985-06-28 Pending JPS628639U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985099636U JPS628639U (ja) 1985-06-28 1985-06-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985099636U JPS628639U (ja) 1985-06-28 1985-06-28

Publications (1)

Publication Number Publication Date
JPS628639U true JPS628639U (ja) 1987-01-19

Family

ID=30968698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985099636U Pending JPS628639U (ja) 1985-06-28 1985-06-28

Country Status (1)

Country Link
JP (1) JPS628639U (ja)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5317276A (en) * 1976-07-30 1978-02-17 Amp Inc Integrated circuit package and method of manufacture thereof
JPS55117263A (en) * 1979-02-23 1980-09-09 Amp Inc Lead frame for integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5317276A (en) * 1976-07-30 1978-02-17 Amp Inc Integrated circuit package and method of manufacture thereof
JPS55117263A (en) * 1979-02-23 1980-09-09 Amp Inc Lead frame for integrated circuit

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