JPS628646U - - Google Patents
Info
- Publication number
- JPS628646U JPS628646U JP10060985U JP10060985U JPS628646U JP S628646 U JPS628646 U JP S628646U JP 10060985 U JP10060985 U JP 10060985U JP 10060985 U JP10060985 U JP 10060985U JP S628646 U JPS628646 U JP S628646U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- conductive layer
- glass substrate
- thick film
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Description
図は本考案の一実施例を示す断面図。
符号の説明、１…ガラス基板、２…グレーズ層
、３…導電層、４…ダイパツト部、５…ＩＣ、６
…金ワイヤー。
The figure is a sectional view showing an embodiment of the present invention. Explanation of symbols: 1... Glass substrate, 2... Glaze layer, 3... Conductive layer, 4... Die pad portion, 5... IC, 6
...gold wire.
Claims (1)
トを印刷ののち、フオトリソエツチング等により
導電層を形成する厚膜混成集積回路において、 前記導電層のボンデイングパツト部と前記ガラ
ス基板の間に低融点のガラスペーストによるグレ
ーズ層を設けたことを特徴とする厚膜混成集積回
路。[Claims for Utility Model Registration] A thick film hybrid integrated circuit in which a metallo-organic paste is printed on the surface of a glass substrate and then a conductive layer is formed by photolithography or the like, a bonding pad portion of the conductive layer and the glass substrate. A thick film hybrid integrated circuit characterized by having a glaze layer made of a low melting point glass paste provided between the layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10060985U JPS628646U (en) | 1985-07-02 | 1985-07-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10060985U JPS628646U (en) | 1985-07-02 | 1985-07-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS628646U true JPS628646U (en) | 1987-01-19 |
Family
ID=30970589
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10060985U Pending JPS628646U (en) | 1985-07-02 | 1985-07-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS628646U (en) |
-
1985
- 1985-07-02 JP JP10060985U patent/JPS628646U/ja active Pending
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