JPS6286745A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6286745A JPS6286745A JP60227557A JP22755785A JPS6286745A JP S6286745 A JPS6286745 A JP S6286745A JP 60227557 A JP60227557 A JP 60227557A JP 22755785 A JP22755785 A JP 22755785A JP S6286745 A JPS6286745 A JP S6286745A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- molding
- glass cloth
- metal plate
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
- H10W76/10—Containers or parts thereof
- H10W76/17—Containers or parts thereof characterised by their materials
- H10W76/18—Insulating materials, e.g. resins, glasses or ceramics
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
- H10W76/60—Seals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に装置の薄肉化。[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor devices, and particularly to thinning of devices.
小型化を容易にし、かつ寸法安定性、生産性及び歩留り
を向上させることのできる半導体装置の封止構造に関す
るものである。The present invention relates to a sealing structure for a semiconductor device that facilitates miniaturization and improves dimensional stability, productivity, and yield.
一般に、半導体チップなどが取付けられ配線パターンが
形成された回路基板は、水分や不純物の介入を防止し耐
湿性、耐iNj撃性をもたせるために、合成樹脂などに
よるポツティングあるいは成形物などによる封止が行わ
れる。ところが合成樹脂によるポツティングでは、樹脂
の構成や厚さが不均一となり加熱や封止樹脂の硬化収縮
によってそりが生じるという問題があった。このため、
最近では金属やセラミック、プラスチックの成形品など
のキャップを被せて封止を行うという方法が注目されて
いる。In general, circuit boards on which semiconductor chips and the like are mounted and wiring patterns formed are potted with synthetic resin or sealed with molded materials to prevent the intervention of moisture and impurities and to provide moisture resistance and iNj impact resistance. will be held. However, potting made of synthetic resin has a problem in that the composition and thickness of the resin are non-uniform and warpage occurs due to heating and curing shrinkage of the sealing resin. For this reason,
Recently, a method of sealing by covering the cap with a molded product of metal, ceramic, or plastic has been attracting attention.
第3図は従来のキャンプ方式による封止構造を示した一
例である。図において、■は基板、2は配線パターン、
3は導電板、4は導電性ペースト、5は半導体チップ、
6はボンディングワイヤ、7はキャップ部、8は接着剤
である。FIG. 3 shows an example of a conventional camp-type sealing structure. In the figure, ■ is the board, 2 is the wiring pattern,
3 is a conductive plate, 4 is a conductive paste, 5 is a semiconductor chip,
6 is a bonding wire, 7 is a cap portion, and 8 is an adhesive.
(発明が解決しようとする問題点〕
従来の半導体装置は以上のように構成されているので、
ギヤ・7ブ部7は半導体チップ5、ポンディングワイヤ
6、配線パターン2などに接することがないように、キ
ャップ高さ、キャップ幅を検討し、また基板との接着を
良好にするため、接着面を検討して設計し、プレス、射
出成形などの成形法を用いて成形する必要があった。そ
のため工程が増えるとともにコストが上がり、生産性を
損なうという問題があった。また接着剤8には一般にエ
ポキシなどの樹脂を液状で用いるが、これは加熱硬化を
行う際に一度該樹脂の粘度が下がり、該樹脂が封止内部
に侵入し、ワイヤボンディング、半導体チップなどに達
し、硬化収縮によりストレスがかかり、ワイヤボンディ
ングの断線、半導体チップのわれなどの故障を引き起こ
す。また接着剤のたれにより接着剤が外部にはみ出し寸
法IN度がでない、接着剤の量によりキャップの高さが
均一でなくなるなどの問題があった。(Problems to be solved by the invention) Since the conventional semiconductor device is configured as described above,
The gear/7 part 7 should be carefully designed to avoid contact with the semiconductor chip 5, bonding wire 6, wiring pattern 2, etc. by considering the height and width of the cap, and to ensure good adhesion to the board. It was necessary to consider and design the surface, and then mold it using molding methods such as pressing and injection molding. As a result, the number of steps increases, the cost goes up, and productivity suffers. In addition, the adhesive 8 generally uses a liquid resin such as epoxy, but when it is heated and cured, the viscosity of the resin decreases and the resin enters the sealing interior, causing wire bonding, semiconductor chips, etc. The hardening shrinkage causes stress, which causes wire bonding to break, semiconductor chips to crack, and other failures. In addition, there have been other problems such as the adhesive dripping out and causing the adhesive to protrude to the outside, resulting in an uneven dimension, and the height of the cap becoming uneven depending on the amount of adhesive.
またICカードなどのモジュールの封止を行う場合には
、上記キャンプ形成形物では厚さをそろえるためたとえ
ば第4図のような工夫が必要であった。第4図において
、1〜7は第3図と同一のものであり、9は樹脂、10
は枠である。第4図のような封止方法では、工程が増え
るとともに、ICモジュールの寸法が枠の分だけ大きく
なり、極力小型化しなければならない場合には大きな問
題となっていた。Further, when sealing a module such as an IC card, it is necessary to take measures as shown in FIG. 4, for example, in order to make the thickness of the camp-forming moldings uniform. In Figure 4, 1 to 7 are the same as in Figure 3, 9 is resin, 10 is
is a frame. In the sealing method as shown in FIG. 4, the number of steps is increased and the dimensions of the IC module are increased by the frame, which is a big problem when miniaturization is required as much as possible.
本発明は上記のような問題点を解消するためになされた
もので、作業性及び歩留りを向上でき小型化の容易な半
導体装置を得ることを目的とする。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device that can improve workability and yield and can be easily miniaturized.
この発明にかかる半導体装置は、ガラスクロスに樹脂を
含浸して半硬化させ、これを回路基板上の回路素子を囲
むように配置して側壁を形成し、該側壁上に上記回路素
子を覆う平板状成形物を配置し、加熱により上記側壁を
完全に硬化するとともに該側壁と上記回路基板及び上記
平板状成形物とを接着したものである。In the semiconductor device according to the present invention, a glass cloth is impregnated with a resin and semi-cured, and this is arranged to surround a circuit element on a circuit board to form a side wall, and a flat plate covering the circuit element is placed on the side wall. The side wall is completely cured by heating, and the side wall, the circuit board, and the plate-like molded product are bonded to each other.
(作用〕
この発明においては、回路基板上の回路素子をガラスク
ロスに樹脂を含浸し半硬化したものと平板状の成形物と
で封止するようにしたから、成形物を容易に作成できる
とともに、接着機能を持つ樹脂を所望の状態に半硬化さ
せ、これにより樹脂のたれを少なくして封止を行なうこ
とができる。(Function) In this invention, since the circuit elements on the circuit board are sealed with semi-cured glass cloth impregnated with resin and a flat molded product, the molded product can be easily produced and By semi-curing the resin having an adhesive function to a desired state, sealing can be performed with less resin dripping.
以下、本発明の一実施例を図について説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第1図は本発明の一実施例による半導体装置の封止構造
の断面図を示し、図において、1〜6は第3図と同一の
ものであり、1)はガラスクロスに樹脂を含浸し樹脂の
たれを少なくするように半硬化させたもので半導体チッ
プを保護し基板と金属板とを接着するプリプレグ枠であ
る。これは例えば通常市販のエポキシ樹脂(分子量約3
00〜2000のもの)、硬化剤(例えばジシアンジア
ミド)、及び公知の触媒(三級アミン、イミダゾール類
など)を溶剤(例えばジメチルホルムアミド、メチルエ
チルケトン、メチルセロソルブなど)で適当に希釈した
ものをガラスクロスに塗布または含浸し、その後、これ
を加熱乾燥したものである。FIG. 1 shows a cross-sectional view of a sealing structure for a semiconductor device according to an embodiment of the present invention. In the figure, 1 to 6 are the same as in FIG. 3, and 1) is a glass cloth impregnated with resin. This is a prepreg frame that is semi-cured to reduce resin dripping, protects semiconductor chips, and bonds substrates and metal plates. This is, for example, a commercially available epoxy resin (molecular weight approximately 3
00 to 2000), a curing agent (e.g. dicyandiamide), and a known catalyst (tertiary amine, imidazole, etc.), diluted with a solvent (e.g. dimethylformamide, methyl ethyl ketone, methyl cellosolve, etc.), and then put it on a glass cloth. It is coated or impregnated and then heated and dried.
また12は平板状に成形され、半導体チップを外部から
のストレスから保護し、水分などの介入を防ぐ金属板、
13は上記金属板12とボンディングワイヤや配線パタ
ーンとの接触を防ぐため該金属板12に形成されたポリ
マ一層である。In addition, 12 is a metal plate formed into a flat plate shape, which protects the semiconductor chip from external stress and prevents moisture from entering.
Reference numeral 13 denotes a single polymer layer formed on the metal plate 12 to prevent contact between the metal plate 12 and bonding wires or wiring patterns.
次に作用効果について説明する。 一本実施例では、
プリプレグ枠1)が従来槽、造のキャップ部側面となり
、かつ基板1及びポリマーコーディングした金属板12
に接着する機能を持つ。このため成形物の立体的加工お
よびその接着面を必要としないことから、加工が容易と
なるとともに、接着剤が不要となり、そのスペースが省
略でき、小型化が可能となる。また上記プリプレグ枠1
)の樹脂を所望の半硬化状態にすることに防止し、寸法
精度を向上することができる。さらに上記樹脂の硬化材
及び触媒を適宜選択することにより所望の低温短時間硬
化を行なうこともでき、これによってさらに作業性を向
上させることができる。またプリプレグ枠が絶縁性を有
するため、たとえ配線パターンに接触しても放電の問題
がなく、歩留りをあげることができる。Next, the effects will be explained. In one embodiment,
The prepreg frame 1) becomes the side surface of the cap part of the conventional tank structure, and the substrate 1 and the polymer-coated metal plate 12
It has the function of adhering to. This eliminates the need for three-dimensional processing of the molded product and its adhesive surface, which facilitates processing, eliminates the need for adhesive, saves space, and allows for miniaturization. Also, the above prepreg frame 1
) can be prevented from reaching the desired semi-cured state, and dimensional accuracy can be improved. Furthermore, by appropriately selecting the curing agent and catalyst for the resin, desired low-temperature and short-time curing can be performed, thereby further improving workability. Moreover, since the prepreg frame has insulating properties, there is no problem of discharge even if it comes into contact with the wiring pattern, and the yield can be increased.
第2図は本発明の他の実施例を示し、図中l〜13は第
1図と同一のものであり、この実施例では半導体チップ
5が半導体基板1に埋めこまれている。このような構成
においても上記実施例と同様な効果が得られる。FIG. 2 shows another embodiment of the present invention, in which numerals 1 to 13 are the same as in FIG. 1, and in this embodiment, a semiconductor chip 5 is embedded in a semiconductor substrate 1. Even in such a configuration, the same effects as in the above embodiment can be obtained.
なお、上記両実施例では、プリプレグ枠として通常市販
のエポキシ樹脂、硬化剤、触媒を溶剤で適当に希釈した
ものをガラスクロスに塗布または含浸し半硬化したもの
を用いたが、これは接着強度にすぐれ、かつ耐熱性、耐
湿性などにすぐれたものであればよい。In both of the above examples, the prepreg frame was semi-cured by coating or impregnating glass cloth with a commercially available epoxy resin, curing agent, and catalyst appropriately diluted with a solvent. Any material may be used as long as it has excellent heat resistance, moisture resistance, etc.
また接着強度に関しては、プリプレグ樹脂組成物にフェ
ノキシ樹脂などの高分子量組成物を添加することによっ
て、非架橋性のリニア成分が架橋網目中に介在し、樹脂
に可撓性をもたせることができ、接着強度をあげること
も可能である。Regarding adhesive strength, by adding a high molecular weight composition such as phenoxy resin to the prepreg resin composition, a non-crosslinkable linear component is interposed in the crosslinked network, making it possible to impart flexibility to the resin. It is also possible to increase the adhesive strength.
また、上記両実施例では平板状成形物として金属を用い
たが、これは薄くても強度があり、耐熱性、耐湿性にす
ぐれたセラミック、プラスチックなどであればよく、錆
などに強く、磁気を帯びないステンレス(SUS304
)のようなものはより好ましい。Furthermore, in both of the above examples, metal was used as the flat plate-shaped molded product, but it may be made of ceramic, plastic, etc., which is thin but strong, has excellent heat resistance and moisture resistance, is resistant to rust, and is magnetic. Stainless steel (SUS304
) is more preferable.
また、上記両実施例では基板と金属板との間は中空であ
ったが、この部分には、外部からのストレスを緩和する
ことができ、外部にストレスを与えることが少ないゲル
状の樹脂を封入してもよい。In addition, in both of the above embodiments, there was a hollow space between the substrate and the metal plate, but this part was filled with a gel-like resin that could alleviate stress from the outside and give less stress to the outside. May be enclosed.
以上のように本発明によれば、半導体チップおよび配線
パターン、その他の回路素子をガラスクロスに樹脂を含
浸して半硬化したものと平板状成形物とで封止するよう
にしたので、半導体チップ、ボンディングワイヤの保護
、耐湿性、耐衝撃性の向上だけでなく、キャップ方式の
成形物の成形工程の省略、装置の厚さの均一化、ICモ
ジュールの小型化、接着剤のたれによる故障の防止、寸
法行うことができる。As described above, according to the present invention, semiconductor chips, wiring patterns, and other circuit elements are sealed with semi-cured glass cloth impregnated with resin and a flat molded product. In addition to protecting bonding wires, improving moisture resistance, and impact resistance, it also eliminates the molding process of cap-type molded products, makes the device thickness uniform, downsizes IC modules, and prevents failures due to adhesive dripping. Prevention, dimensions can be done.
第1図は本発明の一実施例に係る半導体装置を示す断面
図、第2図は他の実施例装置を示す断面図、第3図、第
4図はそれぞれ従来装置の一例を示す断面図である。
図において、1は基板、2は配線パターン、3は導電板
、4は導電性ペースト、5は半導体チップ、6はボンデ
ィングワイヤ、1)はプリプレグ枠、12は金属板、1
3はポリマ一層である。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view showing another embodiment of the device, and FIGS. 3 and 4 are sectional views each showing an example of a conventional device. It is. In the figure, 1 is a substrate, 2 is a wiring pattern, 3 is a conductive plate, 4 is a conductive paste, 5 is a semiconductor chip, 6 is a bonding wire, 1) is a prepreg frame, 12 is a metal plate, 1
3 is a single layer of polymer. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
用いて回路素子を搭載した回路基板上に該回路素子を囲
むように側壁を形成し、 該側壁上に上記回路素子を覆う平板状成形物を配置し、 加熱により上記側壁を完全に硬化するとともに該側壁と
上記回路基板及び上記平板状成形物とを接着してなるこ
とを特徴とする半導体装置。(1) A side wall is formed to surround the circuit element on a circuit board on which a circuit element is mounted using semi-cured glass cloth impregnated with a resin, and a flat plate-like material is formed on the side wall to cover the circuit element. 1. A semiconductor device comprising: placing a molded product; heating the side wall to completely cure the side wall; and adhering the side wall to the circuit board and the flat molded product.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60227557A JPS6286745A (en) | 1985-10-11 | 1985-10-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60227557A JPS6286745A (en) | 1985-10-11 | 1985-10-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6286745A true JPS6286745A (en) | 1987-04-21 |
Family
ID=16862770
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60227557A Pending JPS6286745A (en) | 1985-10-11 | 1985-10-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6286745A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5550403A (en) * | 1994-06-02 | 1996-08-27 | Lsi Logic Corporation | Improved laminate package for an integrated circuit and integrated circuit having such a package |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5411671A (en) * | 1977-06-27 | 1979-01-27 | Nec Corp | Sealing method of semiconductor device |
-
1985
- 1985-10-11 JP JP60227557A patent/JPS6286745A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5411671A (en) * | 1977-06-27 | 1979-01-27 | Nec Corp | Sealing method of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5550403A (en) * | 1994-06-02 | 1996-08-27 | Lsi Logic Corporation | Improved laminate package for an integrated circuit and integrated circuit having such a package |
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