JPS6286765A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To elevate the barrier of a gate electrode part by a method wherein a thin film of impurity which provides a conductivity type different from that of the 1st semiconductor layer is formed on the 1st semiconductor layer by performing an evaporation and a heat treatment for impurity diffusion. CONSTITUTION:A nondoped gallium arsenite layer 2, a nondoped gallium-aluminum arsenite layer 3, an N-type gallium-aluminum arsenite layer 4 and an N-type gallium arsenite layer 5 are successively formed and laminated on a semi-insulating gallium arsenite substrate 1 by a vapor phase deposition method and further a film 6 of zinc, which is P-type impurity, is evaporated. If this semiconductor device is subjected to a heat treatment at 250-350 deg.C, the zinc is diffused into the semiconductor layer 5 to form a P-type conductive layer 6' near the surface. Further, after a gate electrode 7, a source electrode 8 and a drain electrode 9 are formed, the P-type semiconductor layer 6' is removed by etching except the part directly under the gate electrode. Therefore, as the P-type semiconductor layer 6' is provided under the gate electrode only, the height of the barrier of the gate electrode part can be made to be higher than the surface potential between the source and the gate. With this constitution, even in a normally-OFF type FET, increase of source resistance can be suppressed.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, particularly a semiconductor device having a shallow φp-n junction. In particular, field effect transistors (F
In ET), the emphasis is on increasing the speed, and efforts are being made to shorten the gate length, source-gate distance, and reduce the element size by making the active layer thinner.

21-1 (Japanese Journal of
Applied Physics, Vol 2 L
8upplement 21-1.1982) As shown in the document by Niss and Hiyamizu et al. published in Page 161, recesses are used to create normally-off fiFBTs to reduce source resistance and improve characteristics.

However, as the gate length becomes shorter, high process controllability is required, and problems arise with threshold control and gate breakdown voltage due to the recess process.Furthermore, as integration increases, variations between devices increase, resulting in lower yields. As a countermeasure for this problem, as shown by Ohata et al. in the Proceedings of the 31st Japan Society of Applied Physics, Spring 198≠, p. By intervening instead, it is possible to make the barrier height of the gate electrode part higher than the surface potential between the source and gate, and it is possible to raise the threshold without increasing the resistance between the gate and the source. Become.

The fabrication of such a structure is carried out by molecular beam epitaxial method (MBB).
) method is used to continuously grow a highly doped active layer and a semiconductor layer of a 4-voltage type different from that semiconductor layer.In particular, gallium and elemental field effect transistors having a 7'Lm active layer are used. In the case of fabrication, the PM layer is formed continuously after the formation of the active layer.

(Problem to be Solved by the Invention) However, when an active layer is formed using other methods such as vapor phase growth and then a PFI layer is grown using the MBB method, the crystal interface is exposed in the air, so the n-layer There is a problem that a high resistance layer is formed at the interface between the active layer and p/-.Also, a complicated process of fixing the back side of the substrate to a substrate holder with indium etc. is also added.The purpose of the present invention is to A different conductive plate region or a region smaller than the carrier concentration of the active layer is formed in the active layer by a simple method without epitaxial growth of a type semiconductor layer, and the barrier height of the gate electrode part is adjusted to the surface between the source and gate. To be higher than 4th placefj
:1. An object of the present invention is to provide a method for wiring a semiconductor device that enables IJ.

(Another means to solve the problem) In the process of forming the barrier of the gate electrode part in the process of the present invention, an impurity source lA film having a conductivity type different from that of the first semiconductor layer is formed. This is a method of manufacturing a semiconductor device, which is characterized in that it includes a step of forming an impurity on a first semiconductor layer and a step of performing heat treatment for diffusing the impurity.

(Function) A quaternary layer is formed on the first semiconductor layer by a method such as rapidly increasing impurity to have a conductivity xm different from that of the first semiconductor layer, and heat treatment is performed for impurity diffusion. Impurities diffuse near the surface of the chihiro body, and electrical compensation occurs in that region. Therefore, in this region, there is a layer different from the operating layer.
A region of L y or a region p smaller than the carriers of the active layer is formed. As a result, one function is that the height is equivalent to #4, in which a semiconductor layer containing a 4m type impurity, which is different from that of the semiconductor layer, is epitaxially grown, making it possible to raise the barrier of the gate electrode part (Example) A description will be given below using an example using a vapor deposition method according to the illustrations.

Figures 1 and 2 show high-speed electron channels at the Peter junction interface with different electron affinities. Taking PET (DH structure) as an example, a p-type semiconductor layer is formed on an n-type gallium umbrella semiconductor layer without using the epitaxial growth method. The cross-sectional structure of the formed example element is shown using Jfr-.

What about Figure 1 (a)? FIG. 2 is a cross-sectional view showing a # film formed by vaporizing zinc as a p-type impurity on an L-type gallium silicon layer. On a semi-insulating gallium substrate 1, a dinon-doped potassium target layer 2 of 7000 angstroms was formed by vapor phase growth, a non-doped gallium aluminum island layer 3 of 50 angstroms with an aluminum composition ratio of 0.3, and an A-type gallium aluminum layer. cable/*4 to 300 angstroms, r
1m, a 300 angstrom thick gallium oxide layer 5 is formed, and zinc m6f, which is a p-type impurity, is further deposited.

This tosa nm impurity'1) aLItU2 X l 0
Figure 1(b) is a cross-sectional view showing the state of a semiconductor device with a holed structure after heat treatment at 250 to 50°C.
As is clearer, after the heat treatment, the zinc deposited on the surface diffuses into the semiconductor layer 5, forming p-type conductivity l-6' in a region of 100 angstroms near the semiconductor surface. FIG. 1C is a cross-sectional view showing a state in which gate electrode 7, source electrodes 8, and drain electrodes 8, 9 are further formed.0 The PII semiconductor layer other than directly under the gate electrode is removed by etching. Therefore, the ptJ1 conductor layer 6' is formed only for the gate electrode.

Therefore, making the barrier height of the gate electrode portion higher than the surface potential between the source and gate becomes the aJ function.

Figure 2 shows the relationship between carrier concentration and depth from the surface after heat treatment.Due to the diffusion of zinc, a p-type semiconductor layer is formed with a thickness of 100 angstroms on the surface.If such a p-type semiconductor layer was used, The threshold voltage in the case is around 0 volts or −0.7 to the threshold voltage without zinc diffusion.
An increase in the voltage of about 9 volts is observed, which indicates that the resistance between the source and gate has been significantly lowered.

Furthermore, a mutual conductance equivalent to that of an FET whose p-type semiconductor layer is formed by MBEm can be obtained, and an extremely good PE
It turned out to be T%.

(Effects of the Invention) As is clear from the above explanation, according to the present invention, the barrier distance of the gate electrode portion can be made into a surface area between the source gate and the surface of the normally-off type. Also in FIT.

It has the advantage of being able to suppress the increase in source resistance, and has a clear effect of improving the performance of semiconductor devices compared to the conventional method.

[Brief explanation of drawings]

FIGS. 1(a) to (C) are device cross-sectional views showing an example of the steps of the semiconductor device @Q manufacturing method of the present invention. FIG. 2 is a diagram showing the carrier concentration and the depth from the surface FIG. 131. Medium insulating gallium, boron substrate, 2... non-doped gallium-JjtJ layer, 3... doped gallium aluminum arsenide layer, 4... n-type gallium aluminum region 15... n-gallium Attendance Bureau, 6...p
Type gallium phosphatide 1eJ, 7...gate, 8...source, 9...dray bud 1 Figure (α) (b) (C)

Claims (1)

[Claims] A step of forming an impurity having a conductivity type different from that of the first semiconductor layer between the first semiconductor layer and the gate electrode in the step of forming a barrier of the gate electrode portion on the first semiconductor layer; A method for manufacturing a semiconductor device, comprising the step of providing heat treatment for diffusion.