JPS6286766A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To elevate the barrier of a gate electrode part by a method wherein a thin film of impurity or material containing the impurity which provides a conductivity type different from that of the 1st semiconductor layer is formed on the 1st semiconductor layer by performing evaporation, and a gate electrode is formed followed by a heat treatment. CONSTITUTION:A nondoped gallium arsenite layer 2, a nondoped gallium- aluminum arsenite layer 3, an N-type gallium-aluminum arsenite layer 4 and an N-type gallium arsenite layer 5 are successively formed on a semi-insulating gallium arsenite substrate 1 by a vapor phase deposition method and a film 6 of beryllium, which is P-type impurity, is evaporated. Then aluminum, which is metal for a gate electrode, is evaporatted and etched to form the gate electrode 7 and further ohmic metal layers 8 and 9 are evaporated. If this semiconductor device is subjected to a heat treatment at 350-450 deg.C, the beryllium is thermally diffused and a P-type conductive layer 6' is formed and, at the smae time, excellent ohmic contacts 8' and 9' are formed. Therefore, the height of the barrier of the gate electrode part can be made to be higher than the surface potential between the source and the gate. With this constitution, even in a normally-OFF type FET, increase of source resistance can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having a shallow pn junction type gate electrode.

(Prior art) Semiconductor devices have become increasingly highly integrated and fast in recent years, and high speed is particularly important for field effect transistors (FETs) made of ■-V group compounds. - The device size is being reduced by shortening the distance between gates and making the active layer thinner. Furthermore, Japanese Journal of Applied Physics Volume 21. Subliment 21-1 (Japanese
seJourr+al of Applied phy
Olcs, Vol 21゜Supplement 2
1-1, 1982) varnish published on page 161,
Normally off a as shown in the literature by Hiyamizu et al.
By using a recess to create xFg'r, the resistance of the source 1 is reduced 8 and the reinforcement characteristics are improved.

However, as the gate length becomes shorter, the process becomes more expensive.
filJ The ammonium hydroxide recess process causes problems with threshold control and gate breakdown voltage. Furthermore, as integration increases, the dispersion between elements also increases, and as a result, the stability becomes worse.As a countermeasure to this problem, Okawa et al. As shown, by interposing a conductive layer different from the active layer in place of the Schüttke gate without using a recess process, it is possible to raise the barrier height of the gate electrode part higher than the surface potential between the source and gate. 9. It becomes possible to raise the threshold without increasing the resistance between the gate and the source.

The fabrication of such a structure is carried out by molecular beam epitaxial method (MBB).
) method to successively grow a highly doped active layer and a semi-coherent layer of a conductivity type different from that of the semiconductor layer. In particular, in the case of manufacturing a gallium-based field effect transistor having a hemi-shaped active layer, a p-type layer is formed continuously after the active layer is formed.

(Problem to be Solved by the Invention) However, when using other methods such as vapor phase epitaxy to produce an active layer and then grow a p-type layer using the MBB method, the crystal interface is exposed to air. There is a problem in that a high resistance layer is formed at the interface of the 9 layers due to exposure to nJ@.Also, a complicated process of fixing the back surface of the substrate to a substrate holder with isidium or the like is added.

An object of the present invention is to form a region of a different 4111 type in the active layer or a region with a carrier concentration lower than that of the active layer by a simple method without epitaxially growing a semiconductor layer of a conductivity type different from that of the active layer, and to improve the barrier height of the gate electrode portion. An object of the present invention is to provide a method for manufacturing a semiconductor device that allows the surface potential between the source and gate to be higher than the surface potential between the source and gate.

(Means for Solving the Problems) The present invention provides a method for forming a barrier of a gate electrode portion on a first semiconductor layer using a material made of an impurity having a conductivity type different from that of the first semiconductor layer or A method for manufacturing a semiconductor device, comprising the steps of forming a film made of a material containing impurities on a first semiconductor layer, forming a gate electrode, and further performing heat treatment for diffusing the impurities. be.

(Function) A conductor II different from the first semiconductor layer is formed on the first semiconductor layer! An impurity to become a mold or a material containing an impurity is formed in the vicinity of the first semiconductor surface by forming a silicon film by a method such as vapor deposition, forming a gate electrode, and further performing heat treatment for impurity diffusion. The impurity diffuses and electrical compensation occurs in that region. Therefore, in this region, a region with a conductivity type different from that of the active layer or a region with a lower carrier concentration than the active layer is formed.Moreover, as a result of heat treatment performed after the step of forming the gate electrode, a region with a conductivity type different from that of the active layer is formed. It becomes a self-aligned structure in which the region with carrier concentration lower than that of the semiconductor layer or the active layer is limited to the vicinity of the gate electrode.As a result, one function is a semi-integrated structure in which the high concentration layer contains impurities of a conductivity type different from that of the semiconductor layer. This is equivalent to a so-called self-aligned gap electrode in which a layer is epitaxially grown and the epitaxial layer is removed except on the gate electrode, and the barrier of the gate electrode portion can be increased. Furthermore, when epitaxial growth is performed, the process of optimizing the thickness of the active layer cannot be performed, but the present invention has the advantage that the gate electrode portion can be formed after the process of optimizing the thickness. (Example) This will be explained below using an example using a vapor deposition method according to the illustrations.
Figure 1 shows an example of forming a p-type semiconductor M on an n-type gallium semiconducting layer without using the epitaxial growth method using a cross-sectional view of the device. This is a cross-sectional view showing the state in which beryllium, which is a p-type impurity, is vapor-deposited on a gallium substrate layer, and then aluminum is further vapor-deposited. Formation 27,000 angstroms.

Non-doped gallium aluminum back layer 3 with aluminum composition ratio 0.3 50 angstroms, λ type gallium aluminum μ 44300 angstroms.

A specific thickness of 5300 angstroms is formed on 7L-type gallium, and a beryllium film 6, which is a p-type impurity, is further vapor-deposited. At this time, the d degree of 7'L type impurity vJ is 2XIOc
It is m.

FIG. 1(b) shows a state in which aluminum as the gate 'tlL electrode metal is vapor-deposited on (a), aluminum and beryllium are further etched to form gate 1-pole 7, and ohmic metals 8 and 9 are vapor-deposited. 01 which is a cross-sectional view showing
The figure tel shows a semiconductor device having the structure shown in (b) at 350~
FIG. 3 is a cross-sectional view showing the state after heat treatment at 450°C. Immediately below the gate, the deposited beryllium is thermally diffused to form a p-type conductive layer 6' with a thickness of 100 angstroms near the optical surface. At the same time, the source and drain/electrode were also subjected to ohmic heat treatment to achieve good results: Keomic junction s/, 9/
is formed. Therefore, it is possible to make the barrier height of the gate electrode portion higher than the optical surface potential between the source and gate.

When such a p-type semiconductor layer is used, the threshold voltage is around 0 volts, but when beryllium diffusion is not used, the threshold voltage is around 10.7 volts, which is less than the threshold voltage. It can be seen that the resistance between the source and gate has been sufficiently reduced.

Furthermore, a p-type semiconductor layer is formed by the MBB method.
A mutual conductance equivalent to that of
'It turned out to be an ET characteristic.

Figure 2 shows an example in which an alloy of aluminum and zinc is deposited to form pti4'wtt- instead of the method of forming a thin film of aluminum in the embodiment shown in Figure 1. ``μAluminum and zinc alloy, zinc is n
It diffuses into the separated semiconductor to form a p-type 24-conductor layer 6'.

FIG. 3 shows an example in which the recess process and the present invention are used together.
By comparing the threshold voltage of +0.2 volts with the threshold voltage of -0.1 volts for the Schittky gate structure that does not use the present invention, it was possible to manufacture a good normally-off FET. The example is not intended to limit the present invention.In other words, an n-type gallium aluminum silicon field effect transistor is used as an example, but the same effect can be obtained even if other types of gallium aluminum silicon are used or other impurities are used. The diffusion of impurities may be controlled by applying appropriate impurities and applying appropriate heat treatment. source barrier height of
By making the A plane between the gates higher than the 1st position, there is an advantage that it is possible to suppress the increase in source resistance even in the normally-off type II' EIl+, and compared to the conventional method, it is possible to suppress the increase in the source resistance. The young fruit of the child's nth eye is impressive.

[Brief explanation of drawings]

FIGS. 1fs) to 1(c) are diagrams illustrating steps of the back-passing method for a semiconductor device according to the present invention using cross-sectional views of elements. FIGS. 2 and 3 are semiconductor devices d showing other embodiments of the present invention.
It is necessary in the diagram lIr1. l... Insulating gallium old substrate, 2... Non-doped gallium arsenic layer S3... Non-doped gallium aluminum base layer, 4... Type 11 gallium aluminum arsenide, 5... N-layer Gallium backing, 6...Beryllium thin film, 6'...p-type JL11%6"...aluminum/zinc wire, 7...aluminum gate, 8
···sauce. 9...Drain. 1; C(1) (b) CC)

Claims (1)

[Claims] In the step of forming a barrier for a gate electrode portion on the first semiconductor layer, a material made of an impurity that has a conductivity type different from that of the first semiconductor layer, or a material containing the impurity is applied on the first semiconductor layer. 1. A method of manufacturing a semiconductor device, comprising the steps of forming a gate electrode, forming a gate electrode, and performing heat treatment for impurity diffusion.