JPS62876A - Test equipment for semiconductor integrated circuit - Google Patents
Test equipment for semiconductor integrated circuitInfo
- Publication number
- JPS62876A JPS62876A JP60140767A JP14076785A JPS62876A JP S62876 A JPS62876 A JP S62876A JP 60140767 A JP60140767 A JP 60140767A JP 14076785 A JP14076785 A JP 14076785A JP S62876 A JPS62876 A JP S62876A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor integrated
- integrated circuit
- switch means
- signal line
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発BAFi半導体集積回路用試験装置に関するもの
でろる。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a test device for BAFi semiconductor integrated circuits.
第3図は従来の半導体集積回路用試験装置を示すもので
あり2図にh・いて(1)はプログラムに基づき信号5
1(21に試験信号乞印加して、信号線+21 K M
すれ出す電流及び信号線(2膀・ら流れ込む1M、流乞
測定し、この測定値と予じめプログラムされた規格値と
比較し、被測定デバイスの良品、不良品を判別する試験
装置本体、(3]は一端が上記信号線(21に接続され
、上記試験装置を本体(υのプログラムに基づきオン・
オフ制御されるリレーρ為らなるスイッチ手段(4)ン
有した周辺回路、(5)は上記スイッチ手段(4)の他
端に接続されるコンタクトプローブ、(6)は上記試験
装置本体tl+と信号線(2)との間に設けられ。Figure 3 shows a conventional test equipment for semiconductor integrated circuits.
1 (apply test signal to 21, signal line +21 K M
The main body of the test equipment measures the current and signal line (1M flowing from 2 tubes) and compares the measured value with a pre-programmed standard value to determine whether the device under test is good or defective. One end of (3) is connected to the signal line (21), and the test equipment is turned on and off based on the program of the main body (υ).
A peripheral circuit having a switch means (4) consisting of a relay ρ which is turned off, (5) a contact probe connected to the other end of the switch means (4), and (6) a contact probe connected to the test apparatus main body tl+. Provided between the signal line (2) and the signal line (2).
試験装置本体(υから被測定デバイスに印加する電流又
は電圧はモニターするモニタ一点、(7)は被測定デバ
イスである半導体集積回路で、P型の半導(7bン
体基板(1a)とN 型の拡散層謁?有しているもので
ある。The test equipment main body (one monitor point to monitor the current or voltage applied to the device under test from υ, (7) is the semiconductor integrated circuit which is the device under test, P-type semiconductor It has a type of diffusion layer audience.
次に、この様に構成された半導体集積回路用試験装置K
より半導体集積回路を試験する方法について述べる。ま
ず、コンタクトプローブ(5)?波数(7L)
層刈に接触させ、試Ii1.装置本体11ノ?動作させ
ると試験装置本体(11のプログラムに基づきスイッチ
手段(4)がオンされるとともに、信号線+27 IC
所定電圧が#]訓される。その結果、信号線(2J、ス
イッチ手段(旬及びコンタクトプローブ(5)を介して
半導体集積回路(力の拡散層(rb)及び半導体基板(
ra)K電流が流れるか、ろるいは半導体集積回路(7
)の半導体基板(ra)及び拡散層(1b)からコンタ
クトプローブ(5)、スイッチ手段+41及び信号II
+21 Y介して電流が流れ込み、これらのtiv試験
装置本体il+にて測定され、その測定値と予じめプロ
グラムされた規格値と?比較して半導体集積回路(7)
の良品、不良品?判別するものでわる。Next, a semiconductor integrated circuit test apparatus K configured in this manner will be described.
This section describes a method for testing semiconductor integrated circuits. First, contact probe (5)? Wave number (7L) Contact with layer cutting, trial Ii1. Device body 11? When operated, the switch means (4) is turned on based on the program of test device main body (11), and the signal line +27 IC
The predetermined voltage is #]. As a result, the semiconductor integrated circuit (force diffusion layer (RB) and the semiconductor substrate (
ra) K current flows or the semiconductor integrated circuit (7
) from the semiconductor substrate (ra) and diffusion layer (1b) to the contact probe (5), switch means +41 and signal II
A current flows through +21 Y and is measured by these tiv test equipment body il+, and the measured value and the pre-programmed standard value? Comparison of semiconductor integrated circuits (7)
Good or defective products? It depends on what you decide.
また、半導体集積回路(7)とは別の半導体集積回路(
図示せず)を試験する場合には、半導体集積回路(7)
の影11’になくす九め、試験装置本体tllのプログ
ラムに基づきスイッチ手段+41がオフされ、別の半導
体集積回路?測定するためのコンタクトプローブ(図示
せず)と信号線(21との間に接続されたスイッチ手!
R(図示せず)がオンされ、上記と同様にして試験され
ることになる。In addition, a semiconductor integrated circuit (7) different from the semiconductor integrated circuit (7)
When testing a semiconductor integrated circuit (7) (not shown),
At the end of the shadow 11', the switch means +41 is turned off based on the program of the test equipment main body tll, and another semiconductor integrated circuit? A switch connected between a contact probe (not shown) for measurement and a signal line (21!
R (not shown) will be turned on and tested in the same manner as above.
しかるく、上記の様に構成された半導体集積回路用試験
装置ICあっては、スイッチ手段(4]らるいa信号、
vilf21等に何らかの原因により断線あるいは短絡
が生ずると正常な測定条件が得られず1本来良品である
べき半導体集積回路(7)?不良品に、あるいは不良品
でおるべき半導体集積回路(刀を良品に誤判定する危険
性が大であるとともに、良品である半導体集積回路(7
)¥不良品にしてしまうという危険性も伴なうものでb
った。特に、信号線+21に多く・Dスイッチ手段及び
コンタクトプローブ?接続して大量に試験する場合には
非常に大きな問題となるものである。Therefore, in the semiconductor integrated circuit testing device IC configured as described above, the switching means (4) the round a signal,
If a disconnection or short circuit occurs in vilf21 etc. for some reason, normal measurement conditions cannot be obtained and the semiconductor integrated circuit (7), which should have been a good product, will not be able to obtain normal measurement conditions. There is a high risk of erroneously determining that a semiconductor integrated circuit is a defective product or a semiconductor integrated circuit that should be a defective product.
)¥There is also a risk that the product will be defective.b
It was. In particular, there are many signal lines +21, D switch means and contact probes? This becomes a very big problem when connecting and testing a large number of devices.
この発明は上記した点Kffiみてなされたものでるり
、半導体集積回路を試験する前に、スイッチ手段のチェ
ックが行なえ、常圧正常な測定条件の基で試験が行なえ
るようする半導体集積回路用試験装ayt得ることt目
的とするものである。This invention was made in view of the above-mentioned points, and it is a test for semiconductor integrated circuits that allows the switching means to be checked before testing the semiconductor integrated circuit, and allows the test to be performed under normal atmospheric pressure measurement conditions. The purpose is to obtain equipment.
c問題点?解決するための手段〕 この発明に係る半導体集積回路用試験装置は。c Problem? Means to solve] A test device for semiconductor integrated circuits according to the present invention is a test device for semiconductor integrated circuits.
一端に信号線が接続されるスイッチ手段の他端とスイッ
チ手段のチェック信号が印加されるチェック信号線との
間にダイオード全接続したものでらる。A diode is connected between one end of the switch means to which a signal line is connected and the other end of the switch means and a check signal line to which a check signal of the switch means is applied.
この発明においては、ダイオードが半導体集積回路の試
験する前にスイッチ手段へチェック信号を伝達させるこ
とができ、半導体集積回路の試験時には何ら影響7及ぼ
さないように作用する。In this invention, the diode can transmit a check signal to the switch means before testing the semiconductor integrated circuit, and acts so as not to have any influence when testing the semiconductor integrated circuit.
以下にこの発明の一実施例を第1図及び第2図に基づい
て説明する。第1図は半導体集積回路の試験の前のスイ
ッチ手段(4)のオフチェックの状態を示し、第2図は
オンチェックの状態?示し2図洗おいて(8)はカンー
ドがスイッチ手段+41の他端に接続されるダイオード
、(91Fiこのダイオードのアノードに接続され、試
験装置本体(1)からプログラムに基づいてチェック信
号が印加されるチェック信号線、αGは試験装置本体(
1]と信号線(2)との間に設けられ、チェック信号線
+91 K現われる電流又は電圧をモニターする第2の
モニタ一点である0次にこの様に構成された半導体集積
回路用試験装置におけるスイッチ手段(旬のチェック方
法について述べる。まず、コンタクトプローブ(5)ヲ
拡散層(3)K接触させ、試験装置本体(1)を仮試験
動作させると、試験!1tcz本体tl)のプログラム
に基づき。An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 shows an off-check state of the switch means (4) before testing a semiconductor integrated circuit, and FIG. 2 shows an on-check state. As shown in Figure 2, (8) is a diode whose cand is connected to the other end of the switch means +41, (91Fi) is connected to the anode of this diode, and a check signal is applied from the test equipment main body (1) based on the program. The check signal line αG is the test equipment main body (
1] and the signal line (2) and monitors the current or voltage appearing on the check signal line +91K. The switch means (the current checking method will be described below. First, the contact probe (5) is brought into contact with the diffusion layer (3) K, and the test device main body (1) is operated for a temporary test. Based on the program of the test!1tcz main body TL), .
スイッチ手段+41がオフ状態とされて第1図に示す状
態とされる。この時、試験装置本体(1)はダイオード
+9]に対して順方向の電圧乞印加する。例えば信号線
(2)上のモニタ一点(6)にOvが、チェック信号線
+91の第2モニタ一点OGに1vが出力されるように
条件設定されるものである。すると、スイッチ手段(4
)が正常でありオフ状態になっていれば。The switch means +41 is turned off, resulting in the state shown in FIG. At this time, the test device main body (1) applies a forward voltage to the diode +9. For example, conditions are set so that Ov is output to one monitor point (6) on the signal line (2) and 1v is output to one point OG of the second monitor on the check signal line +91. Then, the switch means (4
) is normal and in the off state.
チェック信号線(9]及びダイオード(8)?介して半
導体集積回路(力の拡散層(rb)及び基板(7a)
K電流が流れるが、この電流に、拡散層(1b)及び基
板(ra)は逆方向の接合関係罠なっているため微少リ
ーク電流でしかないものである。従ってモニタ一点(6
1には電流は検知されず、第2モニタ一点Hには微少リ
ーク電流が検知されることになる。一方、スイッチ手段
(旬が何らかの原因でショートされた異常状態であると
、チェック信号線+91からダイオード(8)及びショ
ート状態のスイッチ手段(4)ヲ介して信号Jlt2+
に電流が流れることになる。この電はの値は第2モニタ
一点aσρ・らモニタ一点(61iでの抵抗値に依存さ
れ、スイッチ手段(4)の正常時の微少リーク11It
I!i!より大きなf直となるため、第2モニタ一点Q
りに2ける電流値を測定することにより、スイッチ手段
+41のオフチェックが行なえる。The semiconductor integrated circuit (power diffusion layer (RB) and substrate (7a)
A K current flows, but this current is only a small leakage current because the diffusion layer (1b) and the substrate (ra) have a junction relationship in opposite directions. Therefore, one monitor (6
No current is detected at point 1, and a slight leakage current is detected at one point H of the second monitor. On the other hand, if the switch means is short-circuited for some reason and is in an abnormal state, a signal Jlt2+ is transmitted from the check signal line +91 via the diode (8) and the short-circuited switch means (4).
A current will flow through. The value of this voltage depends on the resistance value at one point of the second monitor (aσρ) and one point of the monitor (61i).
I! i! Since the f angle is larger, the second monitor has one point Q.
By measuring the current value at 2, it is possible to check whether the switch means +41 is off.
次に、試験装置本体(口のプログラムに基づきスイッチ
手段(4)がオン状態とされて第2図の状!1にされる
。すると、スイッチ手段(4)が正常でbリオン状態に
なっていれば、チェック(ff4+41191ρ・らダ
イオード(8)及びスイッチ手段14 ’に介して信号
51+21に’KRが流れ、第2モニタ一点0(IKは
第2モニタ一点8aからモニタ一点(61tでの抵抗値
に依存されたtrlL値が現われる〇一方、スイッチ手
段+41が何らρ・の原因でオフ状態にされた異常状態
でらるとデエ°ツク信号線(91からダイオード(81
ケ介して半導体集積回路(7)の拡敵層(γb)及び基
板(ra)K1!E流が流れ、第2モニタ一点aaには
微少リーク電流の値が現われる。従って、第2モニタ一
点111#cおける電流値を測定するご?−により、ス
イッチ手段(4りのオンチェックが行なえる。Next, the switch means (4) is turned on based on the program in the main body of the test device (see Figure 2). Then, the switch means (4) is normal and in the b-on state. If so, the check (FF4+41191ρ・'KR flows through the diode (8) and the switch means 14' to the signal 51+21, and the resistance value at the second monitor point 0 (IK is from the second monitor point 8a to the monitor point (61t) On the other hand, if the switch means +41 is turned off due to some reason, the trlL value appears.
The enemy expansion layer (γb) of the semiconductor integrated circuit (7) and the substrate (ra) K1! Current E flows, and a minute leakage current value appears at one point aa on the second monitor. Therefore, it is necessary to measure the current value at one point 111#c on the second monitor. - allows on-checking of the switch means (4).
そして、試験装置本体IIIは上記したオフチェックる
るいはオンチェックのどちらか一方でスイッチ手段+4
1が異常でろると判定すると1次に行なわれる半導体集
積回路(7)の試験を停止するようプログラムされてお
り、半導体集積回路(7)のlA@定及びダメージを与
えること?防止しているものでらろ。一方、オフチェッ
ク及びオンチェック両者において、スイッチ手段(41
が正常でりると判定されると、半導体装置本体i17
Fi上記第3図に示したものと同様に半導体集積回路(
〕)の試試験性なうものである◎この時、ダイオード(
8)はスイッチ手段+41とコンタクトプローブ(5)
との接続点に対して逆方向KfM続されているものであ
るから、半導体集積回路(7)の試験に際して何ら影#
を及ぼさないものでるる。なお、さらに正確を期す場合
には、半導体集積回路(7)の試験中、常にダイオード
(8)に逆方向の電圧が印加されるように、@2モニタ
一点四Kg験装瀘本体(!)から電圧を与えるようにし
ても良いものでらる〇
〔発明の効果]
この発明は以上に述べたように、−@に信号線が接続さ
れたスイッチ手段の他端とスイッチ手段のチェック信号
が印加されるチェック信号線との間にダイオードYl!
続したもDとしたので、半導体集積回路の試験前にスイ
ッチ手段のチェックを行なえ、半導体集積回路の誤判定
を少なくできるとともに、半導体集積回路にダメージ?
与えることを抑制できるという効果を有するものでるる
。Then, the test device main body III switches the switch means +4 to either the above-mentioned off-check or on-check.
The program is programmed to stop the primary test of the semiconductor integrated circuit (7) when it is determined that the semiconductor integrated circuit (7) is abnormal, causing damage to the semiconductor integrated circuit (7). It's something that's being prevented. On the other hand, in both off-check and on-check, the switch means (41
If it is determined that the is normal, the semiconductor device main body i17
FiSemiconductor integrated circuit (similar to that shown in Figure 3 above)
])) ◎At this time, the diode (
8) Switch means +41 and contact probe (5)
Since the KfM connection is made in the opposite direction to the connection point with
There are some things that do not affect. If you want even more accuracy, you can use @2 monitors (4 kg per point) to ensure that a voltage in the opposite direction is always applied to the diode (8) during the test of the semiconductor integrated circuit (7). ).〇 [Effect of the Invention] As described above, this invention provides a check signal between the other end of the switch means to which the signal line is connected to -@ and the check signal of the switch means. A diode Yl! is connected between the check signal line and the check signal line to which Yl! is applied.
Since the continuation is also set as D, it is possible to check the switching means before testing the semiconductor integrated circuit, reduce false judgments of the semiconductor integrated circuit, and prevent damage to the semiconductor integrated circuit.
It has the effect of being able to suppress giving.
第1図及び第2図は仁の発明の一実施例を示し第1図は
オフチェック状態の要部回路図、第2図はオンチェック
状態の要部回路図、第3図は従来の半導体集積回路用試
験装[tlに:示すIj1部回−図でろる。
図において(2:は信号線、(4Jはスイッチ手段、(
5)はコンタクトプローブ、(7)は半導体集積回路、
(8)はダイオード、t9)はチェック信号線でろる0
なシ、各図中同−符号は同−又は相当部分を示す。
第1図
1g2図
笥 3 rM
手続補正書(自発)
昭和 鼎 1% 20八
1、事件の表示 特願昭 60−140767号2
、発明ノ名称 半導体’JS vt回路用試験装
に訊補正をする者
事件との関係 特許出願人
住 所 東京都千代田区丸の内二丁目2番3号名
称 (601)三菱電機株式会社代表者 志 岐
守 哉
4、代理人
住 所 東京都千代田区丸の内二丁目2番3号5
、補正の対象
6、補正の内容
(1)明細書第3頁第6行に「流れ込み、これらの電流
を」とあるのを「試験装置本体(1)に流れ込む、これ
らの電流は」と訂正する。
(2)明細書第6頁第2行にr F!j (3)Jとあ
るのを1層(7b)Jと訂正する。
(3)明細書第6頁第5〜6行に「ダイオード(9)」
とあるのを「ダイオード(8)」と訂正する。
(4)図面を別紙のとおり補正する。
以上Figures 1 and 2 show an embodiment of Jin's invention. Figure 1 is a circuit diagram of the main part in an off-check state, Figure 2 is a circuit diagram of the main part in an on-check state, and Figure 3 is a conventional semiconductor. Test equipment for integrated circuits [tl: Ij1 part time-diagram]. In the figure, (2: is a signal line, (4J is a switch means, (
5) is a contact probe, (7) is a semiconductor integrated circuit,
(8) is a diode, t9) is a check signal line.
The same reference numerals in each figure indicate the same or equivalent parts. Figure 1 1g2 Figure 3 rM Procedural amendment (voluntary) Showa Ting 1% 2081, case indication Patent application No. 60-140767 2
, Name of the invention Relationship with the case of a person making amendments to test equipment for semiconductor 'JS VT circuits Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Ambition Gi
Moriya 4, agent address 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo
, Target of amendment 6, Contents of amendment (1) In the 6th line of page 3 of the specification, "these currents flow into" was corrected to "these currents flow into the test device body (1)" do. (2) r F! on page 6, line 2 of the specification. j (3) Correct J to 1st layer (7b) J. (3) "Diode (9)" on page 6, lines 5-6 of the specification
Correct the text to read "diode (8)." (4) Amend the drawing as shown in the attached sheet. that's all
Claims (1)
接続されるスイッチ手段、このスイッチ手段の他端に接
続されるコンタクトプローブ、上記スイッチ手段の他端
と上記スイッチ手段のチェック信号が印加されるチェッ
ク信号線との間に接続されるダイオードを備えた半導体
集積回路用試験装置。A switch means having one end connected to a signal line to which a test signal of the semiconductor integrated circuit is applied, a contact probe connected to the other end of the switch means, and a check signal of the switch means being applied to the other end of the switch means. Test equipment for semiconductor integrated circuits equipped with a diode connected between the check signal line and the check signal line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60140767A JPS62876A (en) | 1985-06-27 | 1985-06-27 | Test equipment for semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60140767A JPS62876A (en) | 1985-06-27 | 1985-06-27 | Test equipment for semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62876A true JPS62876A (en) | 1987-01-06 |
| JPH054034B2 JPH054034B2 (en) | 1993-01-19 |
Family
ID=15276270
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60140767A Granted JPS62876A (en) | 1985-06-27 | 1985-06-27 | Test equipment for semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62876A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5098282A (en) * | 1973-12-26 | 1975-08-05 | ||
| JPS5694965U (en) * | 1979-12-21 | 1981-07-28 |
-
1985
- 1985-06-27 JP JP60140767A patent/JPS62876A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5098282A (en) * | 1973-12-26 | 1975-08-05 | ||
| JPS5694965U (en) * | 1979-12-21 | 1981-07-28 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH054034B2 (en) | 1993-01-19 |
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