JPS628954B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, particularly a method of manufacturing an insulated gate field effect transistor.

In a conventional insulated gate field effect transistor (hereinafter referred to as "MISFET"), one of the main factors that determines the quality of its high frequency characteristics is:
It is the length of the channel formed on the surface of the semiconductor layer between the source and drain of a MISFET, and generally the shorter the length of this channel, the better the high frequency characteristics. However, when the channel is shortened, a punch-through phenomenon is likely to occur due to the expansion of the depletion layer in the channel region, and furthermore, variations in mutual conductance due to bias voltage become large.
In addition, the length of the channel could not be made very short because of problems such as fluctuations in the threshold voltage. Furthermore, it has the above structure
When configuring an integrated circuit using MISFET, the area occupied by the element is determined by the area of the source, drain, and gate electrodes, so in order to reduce the area occupied by the element, it is necessary to reduce the area of each of the electrodes. Although this is necessary, there is a problem in that it is subject to manufacturing technology constraints.

As a solution to the problems of conventional MISFETs as described above, MISFETs have already been proposed that are capable of high-frequency operation and have a new structure and operating principle that enable high-density integration. BSMISFET (Baried Source) has a structure in which the source region is buried within the semiconductor.
Metal Insulator Semiconductor Field Effect
It is an acronym for Transistor. ).

FIG. 1 is a cross-sectional view of a BSMISFET according to the prior art. In FIG. 1, 1 is an N-type semiconductor substrate, 2 is a P-type semiconductor layer formed on the N-type semiconductor substrate 1 by an epitaxial growth method, and 3 is a P-type semiconductor layer.
a gate insulating layer formed on the main surface of the P-type semiconductor layer 2; 4 a gate electrode provided on the gate insulating layer 3; 5 a gate electrode provided on the main surface region of the P-type semiconductor layer 2 adjacent to the gate insulating layer 3; 6 is a drain electrode provided on the drain region 5; 7 is an N ⁺ type source region provided in the boundary region between the semiconductor substrate 1 and the semiconductor layer 2 directly below the gate insulating layer 3; It is. Since the source region 7 is embedded in the semiconductor in this way, the BSMISFET operates differently from a conventional MISFET.

Next, based on the prior art shown in Figure 1,
The operating principle of BSMISFET will be explained. First, when no gate voltage is applied, the energy band structure in the internal direction of the semiconductor immediately below the gate insulating layer 3 is as shown in FIG. 2A, while when a gate voltage V _G is applied, The energy band structure is shown in Figure 2B.
, and a depletion layer is formed in the surface region of the P-type semiconductor layer 2 directly under the gate insulating layer 3. Therefore, by biasing the drain region 5 so as to have a reverse bias with respect to the P-type semiconductor layer 2, and further applying a positive voltage V _G to the gate electrode 4 with respect to the N-type semiconductor substrate 1, the depletion layer is formed inside the semiconductor. It spreads in the P-type semiconductor layer 2 in the direction and reaches the buried source region 7. When the depletion layer reaches the source region 7, carriers are injected from the source region 7 into the depletion layer. The amount of carrier injected naturally depends on the gate voltage V _G . The injected carriers are first accelerated by the gate electric field and travel through the depletion layer, and when they approach the interface between the P-type semiconductor layer 2 and the gate insulating layer 3, they are pulled by the drain electric field and flow into the drain region 5. become.

As is clear from the above description, source region 7
When the depletion layer reaches the source region 7, carriers are injected into the depletion layer from the source region 7, which is formed by the source region 7 directly under the gate insulating layer 3 and the P-type semiconductor layer 2.
The PN junction is forward biased, resulting in
Carriers flow out from the source region 7 into the depletion layer. Therefore, since the amount of carrier is controlled by the gate voltage and not by the drain voltage, the drain voltage-current characteristics of the BSMISFET exhibit characteristics similar to those of the conventional MISFET, as shown in FIG. However, in the BSMISFET, an offset voltage indicated by the symbol V _OF in FIG.
By appropriately selecting _A and the depth d from the gate insulating layer 3 to the source region 7, it is possible to bring the voltage close to almost zero. The relationship between the offset voltage V _OF , the impurity concentration N _A , and the depth d from the gate insulating layer 3 to the source region 7 is approximately given by the following equation from the theory of gate-controlled diodes.

V _OF = qN _A /2Ksε ₀ d ² −2φ _F where φ _F is the fermi potential of the semiconductor layer directly below the gate insulating layer, q is the amount of electron charge, Ks
is the dielectric constant of the semiconductor layer, and ε ₀ is the dielectric constant in vacuum.

As is clear from the above explanation, the carrier flow in the BSMISFET is basically the same as the carrier flow in a punch-through diode, and it can be said that the punch-through current is controlled by the gate voltage. Therefore, since the drain current is a space charge limited current, it is not affected by temperature changes. In addition, in BSMISFET,
Since the carrier travels through the depletion layer between the source and drain at a saturated drift velocity due to the gate electric field and drain electric field, the travel time is extremely short, and furthermore, there is no accumulation effect of the carrier, making it suitable for high-speed operation. It can be said to be a thing.

However, in the BSMISFET, the impurity concentration N _A of the P-type semiconductor layer 2 directly below the gate insulating layer 3 and the depth d from the gate insulating layer 3 to the source region 7
BSMISFET with uniform characteristics is difficult to control because its characteristics vary greatly depending on the
There was a problem that it was difficult to manufacture with good reproducibility.

This invention was made in order to solve the conventional problems as mentioned above, and because it has uniform characteristics,
The purpose of the present invention is to provide a method for manufacturing a semiconductor device that can easily manufacture a BSMISFET.

FIG. 4 shows the basic structure of a BSMISFET manufactured by the method of manufacturing a semiconductor device according to an embodiment of the present invention. In FIG. 4, the same reference numerals as in FIG. A resistive N-type semiconductor substrate 12 is a high resistivity N-type semiconductor substrate 12 formed on the N-type semiconductor substrate 11 by epitaxial growth.
type semiconductor layer (source region), 13a is a first P-type semiconductor region formed by diffusion in the main surface region of the N-type semiconductor layer 12, and 13b is an N-type semiconductor region adjacent to the first P-type semiconductor region 13a. A second P-type semiconductor region 5 is formed by ion-implanting a P-type impurity such as boron into the main surface region of the semiconductor layer 12, and a second P-type semiconductor region 5 is formed by diffusing arsenic or the like into the first P-type semiconductor region 13a. 3 is the second N-type drain region with low resistivity.
This gate insulating layer extends from the surface of the P-type semiconductor region 13b over the first P-type semiconductor region 13a and is formed adjacent to the N-type drain region 5. Note that the first P-type semiconductor region 13a and the second P-type semiconductor region 13b are combined to form the P-type semiconductor region 13.

Next, BSMISFET according to an embodiment of this invention
An example of the manufacturing method will be explained in order of steps with reference to FIG.

First, as shown in FIG. 6A, on one main surface of an N-type semiconductor substrate 11 doped with Sb impurities with a crystal axis <100> specific resistance of 0.005 Ω·cm, a thickness of 3 to 30 cm with a specific resistance of 2 to 4 Ω·cm is deposited. A 6 μm thick N-type semiconductor layer 12 is formed by epitaxial method. Subsequently, a silicon dioxide film 31 is formed on the main surface of the N-type semiconductor layer 12 by thermal oxidation.
A silicon nitride film 32 having a thickness of about 1000 to 2000 Å is formed on top of this by vapor phase growth.

Next, as shown in Figure 6B, finally
The silicon nitride film 32 and the silicon dioxide film 31 are patterned by a known method so that they remain only in the regions intended to become the gate and drain regions of the BSMISFET, and then the remaining silicon nitride film 32 is removed.
Using this as a mask, B ⁺ ions are implanted into the N-type semiconductor layer 12 at 30 to 50 KeV and approximately 1×10 ¹³ to 1×10 ¹⁴ /cm ² to form a P-type semiconductor region 33 for isolation.

Next, as shown in FIG. 6C, oxidation is performed in a high temperature oxidizing atmosphere to form a silicon dioxide film 34 having a thickness of 0.6 to 1.0 μm. At this time, since the silicon nitride film 32 serves as a mask for oxygen atoms, the region directly under the silicon nitride film 32 is not oxidized.

Next, as shown in FIG. 6D, a window is opened in the silicon nitride film 32 on the region where the drain region is to be formed and the silicon dioxide film 31 below it by a known method.
B ⁺ ions are implanted at approximately 10 ¹² to 10 ¹³ /cm ² at 30 to 50 KeV. The dose of B ⁺ ion implantation at this time is
It is necessary to decide by considering the threshold voltage of BSMISFET and the punch-through voltage between source and drain. Subsequently, the junction depth is 2 to 3 in a nitrogen atmosphere.
The P-type semiconductor region 13 is thermally diffused so that it becomes μm.
form a. After that, the P-type semiconductor region 13
As ⁺ ions in a at 50KeV 1×10 ¹⁵ ~5×
An N-type semiconductor region that will become the drain region 5 is formed by implanting approximately 10 ¹⁶ /cm ² . ^The reason why As ⁺ ions are used here is to prevent impurities from deeply diffusing in the subsequent heat treatment process.
Sb ⁺ ions may be used instead of ions. Note that it is desirable to perform annealing treatment in a nitrogen atmosphere after As ⁺ ion implantation.

Next, as shown in FIG. 6E, oxidation is performed in a high-temperature oxygen atmosphere to form a silicon dioxide film 35 with a thickness of approximately 6000 to 10000 Å in the window portion previously described in FIG. 6D. Subsequently, after removing the silicon nitride film 32 and the silicon dioxide film 31 thereunder, thermal oxidation is performed to form the gate insulating layer 3 with a thickness of about 1000 Å. Subsequently, B ⁺ ions are implanted through this gate insulating layer 3 to form a P-type semiconductor region 13b. At this time, the ion implantation energy amount and implantation amount are determined such that the peak value of the implantation amount is located inside the N-type semiconductor layer 12, and the impurity concentration at the peak value is the P-type at that depth, as shown in FIG. Semiconductor region 13a
It is desirable to control the impurity concentration so that it is approximately equal to the impurity concentration.

Next, as shown in FIG. 6F, a polycrystalline silicon layer 36 with a thickness of 4000 nm is formed on the top of the gate insulating layer 3 by vapor phase growth.
After depositing ~5000 Å, it is patterned by a known method, and then phosphorus is thermally diffused over the entire surface.
In addition, in the patterning process of the polycrystalline silicon layer 36, as shown in FIG. 6F, the polycrystalline silicon layer 3
It is desirable that the end portion of the silicon dioxide film 35 be controlled so that the end portion of the silicon dioxide film 35 is in contact with the end portion of the silicon dioxide film 35.

Next, as shown in FIG. 6G, after forming a silicon dioxide film 37 on the entire surface by vapor phase growth, contact holes are formed in the regions where electrodes are to be formed, and drain electrodes 6 and gate electrodes 4 are formed using known electrode forming techniques.
will be established. Note that the source electrode (not shown) can be provided on the lower surface of the semiconductor substrate 11 or the like.

As described above, in this embodiment, the second P-type semiconductor region 13b of the P-type semiconductor region 13, that is,
Since the part immediately below the gate insulating layer 3, which has a large effect on the characteristics of the BSMISFET, is formed by ion implantation, the ion implantation energy and the ion implantation dose can be set independently. The depth of region 13b (that is, the depth from gate insulating layer 3 to source region 12) and its impurity concentration N _A can be easily controlled, and reproducibility can be improved. Furthermore, in this method, an impurity-compensated P-type semiconductor region is created by introducing a P-type impurity into the N-type semiconductor layer 12, so a P-type semiconductor region with high specific resistance can be easily obtained.

Moreover, FIG. 5 is a cross-sectional view showing another BSMISFET manufactured using the method of the present invention. In this BSMISFET, a P-type semiconductor substrate 22 is used as a starting material, and an N ⁺ A type semiconductor region 23 is provided, and this N ⁺ type semiconductor region 23
An N-type semiconductor layer 12 is formed by an epitaxial method on a semiconductor substrate 21 containing a semiconductor substrate. The other parts are the same as the BSMISFET shown in FIG. With this configuration, the P type semiconductor substrate 22 and the source region 12 can be separated, and the wiring of the source region 12 can be connected to the N ⁺ type semiconductor region 2.
3, it is suitable for configuring a memory integrated circuit device, for example.

In addition, in the explanation of the above BSMISFET, the conductivity type of each semiconductor region is fixed to P type or N type, but the conductivity type of each semiconductor region is fixed to the above BSMISFET.
It goes without saying that the present invention can be carried out in the same manner by reversing the above.

As described above, according to the present invention, since the region directly under the gate insulating film where a depletion layer is generated due to the gate voltage is formed by ion implantation, the characteristics of the BSMISFET can be easily controlled. This has the effect of making it possible to manufacture BSMISFET with good reproducibility.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a BSMISFET according to the prior art, FIG. 2 is an energy band diagram for explaining its operation, FIG. 3 is a characteristic diagram of the BSMISFET, and FIG. A cross-sectional view showing the basic structure of the manufactured BSMISFET, FIG. 5 is a cross-sectional view of another BSMISFET manufactured using the method of the present invention, and FIG. 6 is a view showing the manufacture of a semiconductor device according to an embodiment of the present invention. FIG. 7 is a cross-sectional view showing the method step by step, and is a diagram showing the impurity distribution directly under the gate insulating layer of the BSMISFET shown in FIG. 6. In the figure, 3 is a gate insulating layer, 5 is an N-type drain region, 11 and 21 are semiconductor substrates, 12 is a semiconductor layer (source region), 13 is a first P-type semiconductor region, 1
3b is a second P-type semiconductor region with high resistivity formed by ion implantation. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A step of forming a semiconductor layer of a first conductivity type to serve as a source region on a semiconductor substrate, after forming a semiconductor isolation region of a second conductivity type in a predetermined region of the main surface of the semiconductor layer. , forming a first second conductivity type semiconductor region in a portion surrounded by the isolation region; forming a low resistivity drain region in the first second conductivity type semiconductor region; the isolation region; forming a gate insulating layer in a portion surrounded by the drain region so that a portion of the gate insulating layer overlaps with the drain region; implanting ions through the gate insulating layer to form the first second conductivity type semiconductor region on the main surface of the semiconductor layer; 1. A method of manufacturing a semiconductor device, comprising the step of forming a second second conductivity type semiconductor region having a high specific resistance so as to be in contact with the second conductivity type semiconductor region.