JPS629438A - Instruction decoding device - Google Patents

Abstract

PURPOSE:To obtain the microinstructions of each operation independently and simultaneously with each other by giving the independent addresses to each operating microinstruction storing device from an address generating circuit. CONSTITUTION:A microinstruction is decoded by an address generating circuit 2 and the addresses of operating microinstruction storages are delivered to output terminals 2b and 2c. The microinstruction storages 3 and 4 read the operating microinstructions and deliver them to output terminals 3b and 4b. The circuit 2 performs the independent replacement of storage addresses to both storages 3 and 4 and delivers these addresses to the terminals 2b and 2c for the execution of the sequence of each operating microinstruction.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an instruction decoding device used in a microprocessor, particularly a microprocessor using a microprogram control system.

2. Description of the Related Art Conventionally, as shown in FIG. 3, a total nlN microprogram type instruction decoding device stores microinstructions in a single microinstruction storage VA@, and uses an address generation circuit or mapping to store the microinstructions in a single microinstruction storage VA@. Some controlled a large number of operations by providing microinstruction storage addresses from an array.

Problems to be Solved by the Invention As shown in FIG. 4(a), a microinstruction is represented by a combination of an opcode part (operation part) and an operand part (addressing part) (the combination of an opcode and an operand is ( However, in the conventional system, as shown in Figure 4(b), when the operand operations are the same but the opcodes are different, the operand operations for each opcode are performed using a microinstruction. The number of combinations of operations increases as the number of types of operations increases, and the microinstruction storage device is large enough to be enriched with highly functional microinstructions. In addition, in Fig. 4(b), A, B
, C, D represent operands ADD, SUB, LD represent operation codes.

Means for Solving the Problems In order to solve the above problems, the instruction decoding device of the present invention includes:
an address generation circuit that outputs two types of independent addresses corresponding to each of the opcode field and operand field of an input instruction; and two independent microinstruction storage memories each receiving the two types of addresses as inputs. m device, and is configured to connect the outputs of each of the two microinstruction storage devices to obtain a microinstruction output.

Effect: According to the above configuration, microinstructions for each operation can be obtained independently and simultaneously in parallel by providing independent microinstruction storage storage addresses to each operation microinstruction storage storage device from the address generation circuit. .

EXAMPLE Hereinafter, an example of the present invention will be described based on FIGS. 1 and 2.

FIG. 1 is a circuit block diagram of an instruction decoding device according to an embodiment of the present invention, in which 1 is an instruction register, 2 is an address generation circuit, 3 and 4 are microinstruction storage devices, and 5 and 6 are microinstruction registers. .

The instruction register 1 has a macro instruction input terminal 1a and a macro instruction output terminal 1b. The address generation circuit 2 has a macroinstruction input terminal 2a and a microinstruction storage address output terminal 2b.

2C. The operation code microinstruction storage device 3 has a microinstruction storage address input terminal 3a and a microinstruction output terminal 3b.

The operand microinstruction storage device 4 has a microinstruction storage address input terminal 4a and a microinstruction output terminal 4b. The micro-instruction register 5 for the operation code has a micro-instruction input terminal 5a and a micro-instruction output terminal 5b. The operand microinstruction register 6 has one microinstruction input terminal 6a and one microinstruction output terminal 6b.

The macro instruction storage device F3.4 includes the macro instruction storage device F3.4 shown in FIG.
)(b)1. :As shown, opcode ADD, 5LJB
, LD, operand A.

B, C, D, etc. are stored respectively.

The operation of the above configuration will be explained below. The macroinstruction is decoded by the address generation circuit 2, and the microinstruction storage address for each operation is independently output to the microinstruction storage address output terminals 2b and 2C. The microinstruction storage device 23.4, which is given the microinstruction storage address, independently reads out the microinstructions for each operation and outputs them to the microinstruction output terminals 3b and 4b. In order to execute the sequence of micro-instructions for each operation, the address generation circuit 2 updates the storage address of the micro-instructions to each operation micro-instruction storage storage device @3.4. Performed independently for each W13.4 microinstruction storage memory address output terminal 2b
, 2c. In this way, microinstructions for each operation can be obtained independently and concurrently.

Note that the address generation circuit 2 may be configured to generate two independent types of addresses in response to changes in bit positions between the opcode field and the operand field due to the instruction code.

Effects of the Invention As described above, according to the present invention, a microinstruction storage storage device is divided into operations for operation codes and operands, and microinstruction storage storage addresses are assigned to each operation by an address generation circuit. Since independent micro-instructions are obtained, highly functional micro-instructions can be easily realized in a small-scale micro-instruction storage device.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of an instruction decoding device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of a microinstruction storage state in the instruction decoding device, and FIG. 3 is an explanatory diagram of a conventional instruction decoding device. Figure 4 <a) is an explanatory diagram of the structure of the macro instruction;
FIG. 5B is an explanatory diagram of the storage state of microinstructions. 2...Address generation circuit, 3.4...Micro instruction storage storage agent Yoshihiro Morimoto 4N Visit Figure 4 (Musashi-nhshi 4 nki# (g)

Claims (1)

[Scope of Claims] 1. An address generation circuit that outputs two types of independent addresses corresponding to each of the opcode field and operand field of an input instruction; and 2, which receives each of the two types of addresses as input. 1. An instruction decoding device comprising: two independent microinstruction storage devices, and configured to connect the outputs of the two microinstruction storage devices to obtain a microinstruction output. 2. The instruction decoding device according to claim 1, wherein the address generation circuit is configured to generate two independent types of addresses in response to changes in bit positions in the opcode field and the operand field due to the instruction code.