JPS6310567U - - Google Patents
Info
- Publication number
- JPS6310567U JPS6310567U JP1986105051U JP10505186U JPS6310567U JP S6310567 U JPS6310567 U JP S6310567U JP 1986105051 U JP1986105051 U JP 1986105051U JP 10505186 U JP10505186 U JP 10505186U JP S6310567 U JPS6310567 U JP S6310567U
- Authority
- JP
- Japan
- Prior art keywords
- frame
- leads
- plan
- view
- tie bar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
第１図は本考案の第１の実施例の平面図、第２
図は第１の実施例の樹脂成形後の平面図、第３図
は本考案の第２の実施例の平面図、第４図は従来
のリードフレームの平面図、第５図は従来のリー
ドフレームの樹脂成形後の平面図である。 １……放熱板、２……外部リード、３……外部
リード固定用タイバー、４……枠部、５……半導
体素子、６……金属ワイヤー、７……成形樹脂、
８……樹脂成形時のエアベント部、９，９′……
巾広部。
図は第１の実施例の樹脂成形後の平面図、第３図
は本考案の第２の実施例の平面図、第４図は従来
のリードフレームの平面図、第５図は従来のリー
ドフレームの樹脂成形後の平面図である。 １……放熱板、２……外部リード、３……外部
リード固定用タイバー、４……枠部、５……半導
体素子、６……金属ワイヤー、７……成形樹脂、
８……樹脂成形時のエアベント部、９，９′……
巾広部。
Claims (1)
- 半導体装置に使用するリードフレームにおいて
、枠部から延長したリード間を固定するタイバー
の前記リードとは接しない部分に巾広部を設けた
事を特徴とするリードフレーム。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986105051U JPH0521887Y2 (ja) | 1986-07-08 | 1986-07-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986105051U JPH0521887Y2 (ja) | 1986-07-08 | 1986-07-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6310567U true JPS6310567U (ja) | 1988-01-23 |
| JPH0521887Y2 JPH0521887Y2 (ja) | 1993-06-04 |
Family
ID=30979113
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986105051U Expired - Lifetime JPH0521887Y2 (ja) | 1986-07-08 | 1986-07-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0521887Y2 (ja) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5669852A (en) * | 1979-11-09 | 1981-06-11 | Mitsubishi Electric Corp | Lead frame for semiconductor device |
-
1986
- 1986-07-08 JP JP1986105051U patent/JPH0521887Y2/ja not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5669852A (en) * | 1979-11-09 | 1981-06-11 | Mitsubishi Electric Corp | Lead frame for semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0521887Y2 (ja) | 1993-06-04 |