JPS63122151A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS63122151A
JPS63122151A JP26816186A JP26816186A JPS63122151A JP S63122151 A JPS63122151 A JP S63122151A JP 26816186 A JP26816186 A JP 26816186A JP 26816186 A JP26816186 A JP 26816186A JP S63122151 A JPS63122151 A JP S63122151A
Authority
JP
Japan
Prior art keywords
insulating film
photoresist
photoresist layer
contact hole
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26816186A
Other languages
Japanese (ja)
Inventor
Toshihiko Higuchi
俊彦 樋口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP26816186A priority Critical patent/JPS63122151A/en
Publication of JPS63122151A publication Critical patent/JPS63122151A/en
Pending legal-status Critical Current

Links

Landscapes

  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To execute the fine processing of a semiconductor device during a simplified process where a contact hole and an insulating film between wiring layers are formed at the same time. CONSTITUTION:After an insulating film 103 has been formed on an impurity- diffused layer 101 or an underlayer wiring part 102, a photoresist layer 104 is applied on the surface of this assembly. After the photoresist layer has been removed at the part where a contact hole is to be formed at the photoresist layer, the exposed insulating film and the photoresist layer are etched simultaneously at almost the same rate by means of a plasma gas. Then, the thin part of the photoresist layer, i.e. the exposed insulating film where the photoresist layer does not exist at the protruding part of the insulating film, is etched. Finally, almost no uneven part exists as a whole on the insulating film, and a contact hole 105 can be formed.

Description

【発明の詳細な説明】 〔m業上の利用分野〕 本発明は、半導体装置の製造方法において、半導体装置
の不純物拡散層または配!@届の1樟形成した絶縁膜の
一部に、該絶gi上に形成された配線層とのSaをとる
ための大(以下、コンタクトホールと称す、)を形成す
ることさ、記IaWBの間の絶縁膜の凹凸を減少する(
平坦化する)ことで半導体H[の微細加工に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION [Field of industrial application] The present invention relates to a method for manufacturing a semiconductor device, in which an impurity diffusion layer or an impurity diffusion layer of a semiconductor device is used. 1. Forming a hole (hereinafter referred to as a contact hole) in a part of the formed insulating film to connect it to the wiring layer formed on the insulation film, as described in IaWB. Reduce the unevenness of the insulating film between (
This relates to microfabrication of the semiconductor H[by planarization].

〔発明の概要〕[Summary of the invention]

本発明は、半導体装置の製造方法において、フォトレジ
ストと絶!1校をほとんど同じ割合で削る(エツチング
する)ことにより、フンタクトホールの形成と配!!i
I届の間の絶縁膜の平坦化を同時に行なうことにより微
細な半導体装置の配線を行なうものである。
The present invention is a method for manufacturing semiconductor devices that uses photoresists. By cutting (etching) one school at almost the same rate, the formation and layout of the funtact hole is done! ! i
By simultaneously flattening the insulating film between the layers, fine wiring of semiconductor devices can be realized.

(従来の技術) 従来の半導体装置の製造方法では、微細化に対応するた
めの配置!1IAI:!の間の絶縁膜を平坦化し、コン
タクトホールを形成する場合、1)第2図のように液状
絶縁膜を塗布し、固体化した俵、コンタクトホールを形
成する。2)173図のようにコンタクトホールを形成
後、高温処理により全体を平坦化する。あるいは、3)
第4図のように平坦化物質を形成後、全面をエツチング
し、平t11化しくエッチバック)、その後コンタクト
形成する。
(Conventional technology) In the conventional manufacturing method of semiconductor devices, the arrangement to cope with miniaturization! 1IAI:! When flattening the insulating film between the two and forming a contact hole, 1) As shown in FIG. 2, a liquid insulating film is applied and solidified to form a bale and a contact hole. 2) After forming contact holes as shown in Figure 173, the entire surface is planarized by high temperature treatment. Or 3)
After forming a planarizing material as shown in FIG. 4, the entire surface is etched and etched back to make it planar (t11), and then contacts are formed.

笠の方法により微細配線に対応していた。Kasa's method was compatible with fine wiring.

〔発明が解決しようと、するr8Jm点〕しかし、前記
の従来の製造方法では、1)配線層の間に平tH化のた
めの平坦化物質を形成する。
[The r8Jm point that the invention attempts to solve] However, in the above-mentioned conventional manufacturing method, 1) a planarizing material for flattening the tH is formed between wiring layers.

または、2)高温処理、3)2度のエツチング工程、等
の工程の追加により、配l1IVBの間の絶&1膜の平
坦化を計った後コンタクトホールを形成しなければ微細
な配線が行なえないというI!!J I!Iがあった。
Or, by adding processes such as 2) high-temperature treatment, 3) two-time etching process, etc., fine wiring cannot be performed unless a contact hole is formed after planarizing the isolation & 1 film between the interconnects 1, 1, and 1. That's I! ! JI! There was an I.

すなわち、工程増によるコストのlQ大、高温処理のた
めの微細化のむずかしさ等の微細加工上の問題を生じた
。また、配線層の間の絶縁膜の平坦化工程を行なわない
場合、配線のM線、短絡等の問題が生じた。
That is, problems in microfabrication have arisen, such as an increase in cost due to the increase in process steps and difficulty in miniaturization for high-temperature processing. Further, when the process of planarizing the insulating film between the wiring layers is not performed, problems such as M-line wiring and short circuits occur.

そこで、本発明は、上記のような欠点を解決するために
、コンタクト形成の工程でのフォトレジストおよび配I
aFPIの間の絶縁膜のエツチングされる割合をほとん
ど同じにすることにより、コンタクトホールの形成と、
フォトレジストが塗布゛された時の平坦性による配線層
の間の絶R膜の凹凸をすくな(する(平坦化する)こと
をr:4 時に行ない簡略化された工程で半導体装置の
微細カリニを行なうことを目的とする。
Therefore, in order to solve the above-mentioned drawbacks, the present invention has developed
By making the etching rate of the insulating film between the aFPIs almost the same, formation of contact holes and
By reducing (flattening) the unevenness of the absolute R film between the wiring layers due to the flatness when the photoresist is applied, it is possible to improve the fine curvature of the semiconductor device with a simplified process. The purpose is to do something.

(問題点を解決するための手段〕 本発明の半JrJ体装置の製造方法は、a)半導体装置
の不純物拡散層または配線層ゐ上に、絶!!膜を形成す
る工程、 1) )該絶縁股上に、フォトレジストを塗布し、該フ
ォトレジストの一部を除去する工程、C)プラズマ気体
によるエツチングにより、該フォトレジストと該絶縁膜
を同時に削りながら、絶縁膜の下の不純物拡散層または
配線層と、絶縁膜上に形成される配りa届との導通をと
るための穴(コンタクトホール)を形成し、かつ、絶縁
膜の凹凸を少なくする工程、 d)残つたフォトレジストを除去し、絶&IIaの上に
記!a届を形成する工程、からなることを特徴とする。
(Means for Solving the Problems) The method for manufacturing a semi-JrJ device according to the present invention includes: a) a method for manufacturing a semi-JrJ body device of the present invention; ! Step of forming a film: 1)) Step of applying a photoresist on the insulating crotch and removing a part of the photoresist; C) While etching the photoresist and the insulating film at the same time by etching with plasma gas. , a process of forming a contact hole for establishing electrical connection between the impurity diffusion layer or wiring layer under the insulating film and the contact layer formed on the insulating film, and reducing the unevenness of the insulating film. , d) Remove the remaining photoresist and mark on the section &IIa! The method is characterized by comprising a step of forming a notification.

〔実施例〕〔Example〕

以下に本発明の実施例を記す。 Examples of the present invention are described below.

第1I!i0λ)のように半導体装置の不純物拡散層1
01または下層記11102の上に、絶縁膜103を形
成する。第1図b)のように7オトレジスト104を塗
布する。この時、絶縁膜には、凹凸があるが、フォトレ
ジストは、液体の性質により、凹部には厚く、凸部には
、薄く塗布され、全体として凹凸が少ない!l!B形伏
をしている。このフォトレジストのコンタクトホールを
形成する部分のフォトレジストを除去する。
1st I! i0λ), the impurity diffusion layer 1 of the semiconductor device
An insulating film 103 is formed on the lower layer 01 or the lower layer 11102. 7. Apply a photoresist 104 as shown in FIG. 1b). At this time, the insulating film has irregularities, but due to the nature of the liquid, the photoresist is applied thickly to the concave parts and thinly to the convex parts, so there is little irregularity as a whole! l! He is in a B-shape prone position. A portion of this photoresist where a contact hole will be formed is removed.

m1図C)のようにプラズマ気体により、露出した絶&
1膜とフォトレジストを同時に、はとんど同じ割合でエ
ツチングしてゆ(、やがて、フォトレジストの薄い部分
、ずなわら絶lIl膜の凸部のフォトレジストがなくな
り露出した絶縁膜もエツチングされてゆく、この時、絶
縁膜の四部には、まだフォトレジストが残つているため
エツチングされない、最終的には、第1図d)のように
絶縁膜は全体として凹凸がほとんどなくなり、コンタク
トホール106が形成される。さらに良いことには、こ
のようにして形成されたコンタクトホールは、フォトレ
ジスト側面がエツチングされる効果による傾斜がついて
おり、微細な配線に訂利である。第1図C)のように残
ったフォトレジストを除去した後、上層配$1106を
形成する。
As shown in Fig. m1 (C), the exposed
The photoresist film and the photoresist are etched at the same time at almost the same rate (eventually, the photoresist on the thinner parts of the photoresist and the convex parts of the film disappears, and the exposed insulating film is also etched. At this time, the photoresist still remains on the four parts of the insulating film, so it is not etched.Finally, as shown in FIG. is formed. Even better, the contact hole thus formed has a slope due to the effect of etching the side surface of the photoresist, making it suitable for fine wiring. After removing the remaining photoresist as shown in FIG. 1C), an upper layer 1106 is formed.

以上の製造方法により形成された配線層の間の絶縁膜は
、凹凸が少なくほとんど平111なため、1后の配線層
を微細な加工を行なっても、断線や短絡等の問題を起さ
゛ない、また、この方法によって形成されたコンタクト
ホールは、傾斜がついているため、ここでも断線に対し
て強く、さらにコンタクトホールにおける抵抗を低くす
る効果も持つ、とれは、従来技術に比較して而易な製造
方法であり、低コスト化も可能である。また本実施例の
ように加熱工程を一切使用しないので半導体装置の微細
化にもイ「利である。
The insulating film between the wiring layers formed by the above manufacturing method has few irregularities and is almost flat, so even if the next wiring layer is minutely processed, problems such as disconnections and short circuits will not occur. In addition, since the contact hole formed by this method is inclined, it is also strong against disconnection and has the effect of lowering the resistance in the contact hole. This is a manufacturing method that can reduce costs. Furthermore, since no heating process is used as in this embodiment, it is advantageous for miniaturization of semiconductor devices.

〔発明の効果〕〔Effect of the invention〕

本発明の効果は、コンタクトホール形成と、配線層の間
の絶縁膜の形成を同時に行なうことにより、従来技術に
対して工程が簡単であり、製品コストを低(シ、かつ微
細加工できるようになった。
The effects of the present invention are that by forming contact holes and forming an insulating film between wiring layers at the same time, the process is simpler than the conventional technology, the product cost is low, and microfabrication is possible. became.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a)、〜C)は、本発明の半導体装置の製造方法
の実施例として断面構造を工程を追、で示した図。 第2図a)〜C)は、従来技術の液伏絶縁殻を塗布する
工程図、第8図a)〜b)は、従来技術の高温処理によ
る工程図、第4図a)〜d)は、従来技術のエッヂバッ
クによる工程の概略図。 101・・・不純物拡散届 !02・・・本心配線 】03・・・絶縁膜 104・・・フォトレジスト 105・・・コンタクトホール 106・・・1届配線 以   上 出願人 セイコーエプソン株式会社 晃2 目 @3I刃
1A) to 1C) are diagrams showing a cross-sectional structure step by step as an embodiment of the method for manufacturing a semiconductor device of the present invention. Figures 2 a) to C) are process diagrams for applying a liquid sink insulation shell according to the prior art, Figures 8 a) to b) are process diagrams for high temperature treatment according to the prior art, and Figures 4 a) to d). 1 is a schematic diagram of a process using edge back according to the prior art. 101...Notification of impurity diffusion! 02... Lines of concern] 03... Insulating film 104... Photoresist 105... Contact hole 106... 1 notification wiring or more Applicant Seiko Epson Corporation Ko 2nd @ 3I blade

Claims (1)

【特許請求の範囲】 a)半導体装置の不純物拡散口または配線層の上に、絶
縁膜を形成する工程、 b)該絶縁膜上に、フォトレジストを塗布し、該フォト
レジストの一部を除去する工程、c)プラズマ気体によ
るエッチングにより、該フォトレジストと該絶縁膜を同
時に削りながら、絶縁膜の下の不純物拡散層または配線
層と、絶縁股上に形成される配線層との導通をとるため
の穴を形成し、かつ、絶縁膜の凹凸を少なくする工程、 d)残ったフォトレジストを除去し、絶縁膜の上に配線
層を形成する工程、からなることを特徴とする半導体装
置の製造方法。
[Claims] a) Step of forming an insulating film on an impurity diffusion port or wiring layer of a semiconductor device; b) Applying a photoresist on the insulating film and removing a part of the photoresist. c) To establish conduction between the impurity diffusion layer or wiring layer under the insulation film and the wiring layer formed on the insulation crotch while etching the photoresist and the insulation film at the same time by etching with plasma gas. d) removing the remaining photoresist and forming a wiring layer on the insulating film. Method.
JP26816186A 1986-11-11 1986-11-11 Manufacture of semiconductor device Pending JPS63122151A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26816186A JPS63122151A (en) 1986-11-11 1986-11-11 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26816186A JPS63122151A (en) 1986-11-11 1986-11-11 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS63122151A true JPS63122151A (en) 1988-05-26

Family

ID=17454751

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26816186A Pending JPS63122151A (en) 1986-11-11 1986-11-11 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS63122151A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008087430A (en) * 2006-10-05 2008-04-17 Nagoya Oil Chem Co Ltd Manufacturing method for interior materials
US8361912B2 (en) 2000-06-30 2013-01-29 Owens Corning Intellectual Capital, Llc Hood, dash, firewall or engine cover liner

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8361912B2 (en) 2000-06-30 2013-01-29 Owens Corning Intellectual Capital, Llc Hood, dash, firewall or engine cover liner
JP2008087430A (en) * 2006-10-05 2008-04-17 Nagoya Oil Chem Co Ltd Manufacturing method for interior materials

Similar Documents

Publication Publication Date Title
JPH01290236A (en) Method of levelling wide trench
US4007103A (en) Planarizing insulative layers by resputtering
JPH05211241A (en) Constitution body of via and its manufacture
JPH04229625A (en) Manufacture of semiconductor device
JP3348327B2 (en) Multilayer wiring forming method and structure
JPS59158534A (en) Manufacture of semiconductor device
JP2000260871A (en) Manufacture of semiconductor device
JPH01212439A (en) Processing of interlayer film
KR0140733B1 (en) Method of forming dontact in semiconductor device
WO1984004996A1 (en) Process for fabricating semiconductor structures
JP2001176872A (en) Method for manufacturing semiconductor device
JPS6331121A (en) Manufacture of semiconductor device
JPH05226475A (en) Method for manufacturing semiconductor device
KR0147648B1 (en) Method for planarization interlayer insulating film of semiconductor device
JPH09153488A (en) Insulating film structure of semiconductor device and planarization method thereof
JPS6010751A (en) Semiconductor integrated circuit device
JPS6278853A (en) Manufacture of semiconductor device
JP2003023067A (en) Via metal layer forming method and via metal layer forming substrate
JPS63102340A (en) Manufacture of semiconductor device
JPS63102338A (en) Manufacture of semiconductor device
KR960007642B1 (en) Manufacturing method of semiconductor device
JPH04167448A (en) Manufacture of semiconductor device
JPH04280455A (en) Manufacture of semiconductor device
JPH0527275B2 (en)
JPH06140397A (en) Method for forming multilayer wiring