JPS631346U - - Google Patents
Info
- Publication number
- JPS631346U JPS631346U JP9481186U JP9481186U JPS631346U JP S631346 U JPS631346 U JP S631346U JP 9481186 U JP9481186 U JP 9481186U JP 9481186 U JP9481186 U JP 9481186U JP S631346 U JPS631346 U JP S631346U
- Authority
- JP
- Japan
- Prior art keywords
- pad
- diffusion region
- electrode
- surge voltage
- extension electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims 4
- 239000000758 substrate Substances 0.000 claims 2
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
第１図は本考案装置の１実施例の部分平面図、
第２図は第１図中の―部分の拡大断面図であ
る。
５…第１パツド、３，４…第１、第２電源ライ
ン、８，９…延長電極、１１…第１拡散領域部、
１２…第２拡散領域部、１４，１５…第２電極、
１６，１７…導電路。
FIG. 1 is a partial plan view of one embodiment of the device of the present invention;
FIG. 2 is an enlarged cross-sectional view of the portion shown in FIG. 5... First pad, 3, 4... First and second power supply lines, 8, 9... Extension electrode, 11... First diffusion region section,
12... Second diffusion region section, 14, 15... Second electrode,
16, 17... Conductive path.
Claims (1)
、該第１、第２パツドにそれぞれ接続されている
第１、第２電源ラインと、前記第１パツドの近傍
に配設され該第１パツドに付与されるサージ電圧
を前記第２電源サインに側路するサージ電圧側路
手段とを備えてなる保護回路付き半導体装置。 (2) 前記サージ電圧側路手段は前記第１パツド
から延在する延長電極と、該延長電極に接続され
該延長電極下の半導体基板に形成されている第１
拡散領域部と、該第１拡散領域部に隣接して前記
半導体基板に形成されている第２拡散領域部と、
該第２拡散領域部に接続され該第２拡散領域部上
に形成されている第２電極と、該第２電極と前記
第２電源ラインとを連絡する導電路と、を備えて
なることを特徴とする実用新案登録請求の範囲第
(1)項記載の保護回路付き半導体装置。[Claims for Utility Model Registration] (1) First and second pads for supplying power, first and second power lines connected to the first and second pads, respectively; A semiconductor device with a protection circuit, comprising: a surge voltage shunting means disposed near a pad for shunting a surge voltage applied to the first pad to the second power supply sign. (2) The surge voltage bypass means includes an extension electrode extending from the first pad, and a first pad connected to the extension electrode and formed on the semiconductor substrate below the extension electrode.
a second diffusion region formed in the semiconductor substrate adjacent to the first diffusion region;
A second electrode connected to the second diffusion region and formed on the second diffusion region, and a conductive path connecting the second electrode and the second power supply line. Featured utility model registration claims No.
A semiconductor device with a protection circuit as described in (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9481186U JPS631346U (en) | 1986-06-20 | 1986-06-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9481186U JPS631346U (en) | 1986-06-20 | 1986-06-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS631346U true JPS631346U (en) | 1988-01-07 |
Family
ID=30958647
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9481186U Pending JPS631346U (en) | 1986-06-20 | 1986-06-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS631346U (en) |
-
1986
- 1986-06-20 JP JP9481186U patent/JPS631346U/ja active Pending
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