JPS63142402A - Method for data reception from successive comparison type a/d converter - Google Patents

Abstract

PURPOSE:To reduce the probability of erroneous reception by limiting the permission period of reception interruption by a program when conversion data of successive conversion type ADC (A/D converter) is received with serial communication. CONSTITUTION:A successive comparison type A/D converter system consists of a CPU 1, a successive comparison type ADC 2, a serial data line 3, and a serial reception register 4, and the ADC 2 is provided with an address latch 21, a multiplexer 22, a successively comparing register 23, etc. The time from permission of serial reception interruption of an interrupt routine occurring at intervals of a prescribed time to inhibition of serial reception interruption of a serial reception interruption routine is provided by the processing of the CPU 1, and a permission time of reception interruption (about 100mus) is set. Thus, since the CPU 1 does not accept reception interruption even if erroneous data is inputted to the serial reception register 4 by noise in the other period to request reception interruption, the probability of erroneous reception due to noise is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data reception method for receiving conversion data of a successive approximation type A/D converter using a serial reception interrupt.

[Conventional technology]

When the CPU issues a command to start A/D conversion and the successive approximation type A/D converter (hereinafter referred to as ADC) that receives the command outputs converted data serially, a predetermined bit is sent to the serial reception register of the CPU IIJ. A serial interrupt is issued to the CPU at the stage when the number of conversion data has been taken in. CPU
waits for this interrupt, takes in the conversion data, and performs one A/
Complete D conversion.

Figure 3 is a configuration diagram of this type of system, where 1 is the CPU, 2
is a successive approximation type ADC, 3 is a serial data line, and 4 is a serial reception register. An analog input CH (channel) selection signal, AD start signal, and clock signal are output from the CPUI to the ADC2. The ADC 2 holds a 3-bit CH selection signal in an address latch 21, and selects a corresponding analog input (one of CHO to CH7) with a multiplexer 22. Successive approximation register (SAR)
Upon receiving the AD start signal, 23 first applies 1/2 of the maximum reference voltage REF to the D/A converter (DAC) 24,
The analog converted value is compared with the analog input by a comparator 25. Then, through the multiplexer 22, the comparison result of the corresponding channel (1 or 0 depending on the size) is 5.
When input to AR23, 5AR23 receives the next comparison value 2R
EF is given to the DAC 24, and thereafter the comparison value is changed to 2-3 REF, 2' REF, . . . every time a clock is input. Then, when the comparison result for the last comparison value 2-8REF is obtained, a start bit and a stop bit are added to the 8-bit A/D conversion data for 2REF to 2REF, and the data is serially transferred from the shift register 26 to the data line 3. The data is sent and transferred to the serial reception register 4 on the CPU side.

FIG. 4 is a time chart when analog input is AD converted into 8 bits with a clock frequency of 250 KHz. Since one clock period is 4 .mu.s, AD conversion of 8 pins I requires 8.times.4 .mu.5=32 .mu.s, and data transmission requires (8+2).times.4 .mu.5 - 40 .mu.s since one start bit and one stop bit are added. Therefore, after a certain time T (=72 μs) from the rise of the AD start signal, C
A reception interrupt is applied to PU1.

FIG. 5(a) shows the relationship between the clock and serial transfer data, and in this example, the serial reception register 4 can take in data at the falling edge of the clock.

[Problem that the invention seeks to solve]

By the way, as control contents become more complex in electronic control units that control internal combustion engines, there is a demand for faster A/D conversion, and successive approximation type ADCs as described above are increasingly used. However, since serial reception as explained in FIG. 3 is susceptible to noise, there is a strong possibility that erroneous data will be received.

In other words, as shown in Figure 5 (bl), if noise (especially ignition noise) mixes into data line 3 and the level of data line 3 changes temporarily even when A/D conversion data is not being transmitted, This is read as a start bit, resulting in incorrect data being received due to noise.

Generally, on the ADCZ side, a protection measure is taken to pull up the data line 3 so that the output does not change when the AD start signal is not received. Also, from the viewpoint that conversion data will not be sent unless the CPU issues an AD start, the reception interrupt is always accepted.

Therefore, in the case shown in FIG. 5(b), all 1's are erroneously received.

In order to improve this point, conventionally, a filter is provided on the receiving end side of the data line 3 to remove the noise. However, when a filter is used, high-speed transmission is not possible due to its time constant, and control responsiveness cannot be sufficiently improved. Further, a filter using an analog circuit is not preferable because it increases the amount of hardware.

The present invention attempts to reduce the probability of such erroneous reception without using a filter.

[Means for solving problems]

The present invention issues a conversion start command from a CPU to a successive approximation type A/D converter, and upon receiving the command, the converter successively compares an analog input with a reference value and converts it into digital data of a predetermined number of bits. Furthermore, in a method for receiving data from a successive approximation type A/D converter in which a reception interrupt is generated to the CPU when the data is transferred to the serial reception register on the CPU side by serial communication, the reception of reception interrupt by the CPU is converted. This is characterized by being limited to a certain period of time after sending the start command.

[Effect]

If reception of reception interrupts by the CPU is limited to a certain period after sending the conversion start command, even if incorrect data is input to the serial reception register due to noise and a reception interrupt request occurs during another period, Since the CPU does not accept it, the probability of erroneous reception due to noise is significantly reduced. Moreover, C.P.
Since U does not perform unnecessary interrupt processing, the processing time can be kept constant regardless of the presence or absence of noise. Furthermore, since no filter or the like is used, the baud rate does not decrease.

〔Example〕

FIG. 1 is a flowchart showing one embodiment of the present invention, and shows a part of the processing of the CPUI shown in FIG. COMP
1 is an interrupt routine that occurs every 2ms, and "conversion CH upper set sends CH selection signal in Figure 3 and starts rAD conversion"
corresponds to sending an AD start signal. In this example, this A
Enable serial reception interrupt at the same time as D start (conversion start command). FIG. 2 is this time chart.

As shown in FIG. 4, when the transmission of the converted data is completed 72 μs after the start of conversion, a serial reception interrupt occurs at that point. In the serial reception interrupt routine in Figure 1, A
Performs processing associated with the D conversion result, and then disables serial reception interrupts. Therefore, the book (in Ji, the interrupt routine COMP
The time from serial reception interrupt enable in step 1 to serial reception interrupt disable in the serial reception interrupt routine (approximately 100 μs) is the allowable time for reception interrupt, and the other period (2m 5-100 μs) is the time for reception interrupt. is prohibited.

However, considering the failure of ADC2, 20
If no reception interrupt occurs after 0μs, COMP
Step 2 forcibly disables serial reception interrupts so that they do not affect the main routine. This is the broken line in FIG. This 200 μs is a length that takes into consideration the delay in jumping into the serial interrupt routine due to other interrupts, and if that happens, 72 μs+several μs is enough.

〔Effect of the invention〕

As described above, according to the present invention, when receiving conversion data of a successive conversion type ADC via serial communication, the period of permission for reception interrupts is limited by a program, so that erroneous reception due to noise can be avoided without reducing the baud rate. can reduce the probability of

[Brief explanation of the drawing]

Fig. 1 is a flowchart showing an embodiment of the present invention, Fig. 2 is an explanatory diagram of its operation, Fig. 3 is a block diagram of a system for receiving data from a successive approximation type A/D converter, and Fig. 4 is an A/D converter. A time chart of the conversion operation, FIG. 5 is an explanatory diagram of A/D conversion data. In the figure, 1 is a CPU, 2 is a successive approximation type A/D converter, 3 is a serial data line, and 4 is a serial reception register. Applicant Fujitsu Ten Ltd. Representative Patent Attorney Ao Yanagi Minoru 1 Figure 2 Conversion start (+1) Normal Mugi Shin Poem (b) tHe t I Breathing Figure 5

Claims (1)

[Claims] The CPU issues a conversion start command to a successive approximation type A/D converter, and upon receiving the command, the converter successively compares the analog input with a reference value and converts it into digital data of a predetermined number of bits.
Furthermore, in a method for receiving data from a successive approximation type A/D converter in which a reception interrupt is generated to the CPU when the data is transferred to the serial reception register on the CPU side by serial communication, the reception of reception interrupt by the CPU is converted. Successive approximation type A/
How to receive data from a D converter.