JPS63166331A - Output system for ad converter - Google Patents

Abstract

PURPOSE:To prevent malfunction during transmission by sending allowing an AD converter to send the result of AD conversion to a processor while the designated channel information is added and allowing the processor to fetch the channel information being the result of AD conversion when the information is the designated information and not to fetch it when not. CONSTITUTION:The result of AD conversion sent serially is in the unit of 16 bits and channel information is given to 15-12-bit. Up to 16-bit channel is designated with 15-12 bits, that is, 4-bit and sufficient for a conventional application. Moreover, the AD conversion requires the resolution of 8-bit, 10-bit and 12-bit, but the resolution of 16-bit is not called for, then in selecting the serial transmission block as 16-bit, there is a sufficient room to the insertion of the channel information. The channel information is given in the result of AD conversion in this way and the processor checks whether or not the sent channel information is coincident with the designated channel information, and when they are coincident, the result of AD conversion is fetched to evade the malfunction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output method of a multi-channel AD converter that is designated with a channel and performs AD conversion of the designated channel.

[Conventional technology]

In an engine control system using a processor, sensors are placed in each part of the engine, and the outputs of these sensors are taken in to control the engine. Since the processor is a digital type device, if the sensor output is analog, it is AD converted and taken in, and for this purpose an AD converter is usually attached externally.

FIG. 4 shows an outline of this type of AD conversion.

As shown in Figure 4, the analog-to-digital converter ADC
is connected to the processor CPU through signal lines 11 to β3, and one channel to be AD converted from the CPU to the ADC is determined through the signal line 11. Eight DCs have #1. #2. ...
...#n n1 fixed analog input is input, signal line β3
When the activation signal CS is input through the control circuit 1, the designated channel (analog input) is subjected to AD conversion, and when the conversion is completed, the conversion result (digital output) is automatically transmitted to the CPU through the signal line β2. SIN in the figure, 5OO
T indicates serial input and serial output, and channel designation data is also serially transmitted. The ADC includes a multiplexer, and upon receiving a channel designation, the multiplexer selects the designated channel.

[Problem that the invention seeks to solve]

In this way, the processor specifies the channel to be AD converted, and the AD converter converts the AD of the specified channel.
The conversion is performed and the conversion result is sent to the processor. However, when specifying a channel, if noise appears on the signal line β) and the channel specification data is corrupted, the AD converter performs AD conversion on a channel other than the channel specified by the processor. , there is a risk that the conversion result will be sent to the processor.

The processor interprets the sent AD conversion results as those of the designated channel and processes them accordingly, resulting in malfunction. The present invention aims to improve these points and prevent malfunctions.

[Means for solving problems]

The present invention relates to an output method of a multi-channel AD converter (ADC) that is connected to a processor (CPtJ), performs AD conversion on a predetermined channel by the processor, and serially transmits the conversion result to the processor. , Serially transmits the information of the channel to be AD converted sent from the processor to the processor 7 together with the AD conversion result, and the processor compares the serially transmitted channel information with the specified channel information, If there is a match, the serially transmitted AD conversion result is taken in.

[Effect]

According to this method, the AD converter attaches specified channel information and sends the AD conversion result to the processor, and the processor takes it in if the channel information of the sent AD conversion result matches the specified channel information, and if it does not, it takes it in. This prevents malfunctions due to noise mixing during transmission, making it effective for use in engine control systems.

〔Example〕

In the present invention, channel information is included in the AD conversion result that is serially transmitted to the processor. FIG. 2 is a diagram explaining this. The AD conversion result that is serially transmitted is in units of 16 bits, and channel information is stored in a portion of 15 to 12 bits. 15 to 12 bits, that is, 4 bits, can specify up to 16 channels, which is usually sufficient. AD conversion requires resolution of 8 bits, 10 bits, 12 bits, etc., but it does not require resolution of as much as 16 bits. Therefore, if the serial transmission block is 16 bits, channel information can be inserted. There is enough room.

In this way, the channel information is entered in the AD conversion result, the processor checks whether the sent channel information matches the specified channel information, and if it matches, it imports the AD conversion result. , malfunctions can be avoided.

The AD conversion result is serially transmitted from the ADC to the CPU through the signal line β2, but this signal line A2 is always at H (high) level and becomes L (low) level when serial transmission starts. This 1 bit at L level becomes a start bit, followed by 16 pieces of data in this example. Of course, the data is binary data, and its 1 and 0 are represented by H and L, and these H and L are synchronized with the falling edge of the clock.
Reading of the L level is performed at the rising edge of the clock.

The clock source is located on the CPU side and is sent to the ADC through a clock line (not shown). When data transmission is finished, signal line 1
2 becomes H level, which becomes a stop bit.

The processor requests AD conversion at regular intervals, for example, every 2 mS. Since there are a large number of sensors, the AD conversion is performed in order, but since some AD conversion cycles may be long, the channel to be AD converted at that point in time is determined by logic that takes this into account. FIG. 3(a) shows this processing flow. The determined channel CH is stored in the memory and serially transmitted to the ADC through the signal line N+.

In the ADC, this is received in a register and given to the multiplexer to select a channel, and when AD conversion is completed, the contents of the register are passed after the conversion result (in the case of a successive approximation type ADC, it is stored in the successive approximation register). let me,
It is serially transmitted to the CPU through the signal line 12 in the form shown in FIG.

When this serial transmission is completed, an interrupt is generated in the CPU, and the contents of the reception register (not shown) that received this serial transmission data are loaded into the memory (RAM), as shown in Figure 2 (b). In the present invention, the channel number stored in the memory is read out and the ADC
If they match, the above-mentioned capture is performed; however, if they do not match, the channel numbers are not captured and are discarded.

FIG. 1 shows the main parts of the present invention. CH determination, AD conversion, C
The steps up to H comparison are the same as above. If it is a scheduled channel, it will be processed, but this will differ depending on the channel, so CH=1? , cH=2? , . . . judgment blocks follow, and processing specific to that channel is started at the appropriate place. With this processing procedure, if noise occurs during data transmission between the processor and the AD converter and channel information is corrupted, the data will be discarded, thus preventing malfunctions.

FIG. 5 and FIG. 6 show the circuit configuration of an AD converter to which the present invention is applied. MPX is a multiplexer, SAR is a successive approximation register, and a DA converter (not shown) is added to these to form a multi-channel AD converter. ADCL is a launcher for receiving channel information sent from the processor CPU, and LOG is an OR converter for sending the AD conversion result and channel information to the processor CPU.

The OR converter LOC consists of a channel shift register C3R1, a current shift register DSR1, and an OR gate G, as shown in FIG. ADC is the above-mentioned 8ocL, M
Includes PX, SAR, and DAC.

The channel information from the processor taken into the register ADCR becomes the MPX channel selection signal, and also becomes the channel selection signal of the MPX.
It is sent to 3R and used for notification to the processor. The AD conversion result is transferred from register SAR to data register DSR, and sent from this DSR to the processor. C3R,
The shift of DSR is performed by the clock from the processor, and as shown in the figure, the 4-bit channel information (indicated by the ≠ symbol) is shifted from the left end of register C3R, and the data in register DSR (indicated by the cross symbol) is shifted from the right end. As a result of the above shift, first 12 bits from DSR are output, then 4 bits of channel information are output from C3R, and these are sent to the processor CPU.

〔Effect of the invention〕

As explained above, in the present invention, the AD converter attaches specified channel information and sends the AD conversion result to the processor, and the processor takes it in if the channel information of the sent AD conversion result is the specified one. Since it prevents the data from being taken in if it is not present, it is possible to prevent malfunctions due to noise contamination during transmission, making it effective for use in engine control systems.

[Brief explanation of the drawing]

Fig. 1 is a flowchart showing the main part of the output method of the present invention, Fig. 2 is an explanatory diagram of serial transmission data, Fig. 3 is a flowchart of channel determination and comparison procedure, and Fig. 4 shows the connection relationship between ADC and CPU. FIG. 5 and FIG. 6 are block diagrams showing the circuit configuration of the AD converter and details of a part thereof. Applicant Fujitsu Ten Ltd. Representative Patent Attorney Minoru Aoyagi The essentials of the F method of the present invention are shown below. Noah Figure 4

Claims (1)

[Claims] In an output method of a multi-channel AD converter (ADC) that is connected to a processor (CPU), performs AD conversion on a channel specified by the processor, and serially transmits the conversion result to the processor. , Serially transmits the information of the channel to be AD converted sent from the processor to the processor along with the AD conversion result, and the processor compares the serially transmitted channel information with the specified channel information and performs the same. An output method of an AD converter characterized in that, if the serially transmitted AD conversion result is received.