JPH04364623A - Communication speed detection method in start-stop synchronization communication system - Google Patents

Abstract

PURPOSE:To realize the detection of a communication speed rich in the profitability and flexibility by sampling data signal lines without addition of the hardware. CONSTITUTION:The start-stop synchronization communication system implementing the data communication at plural communication speeds through a prescribed communication object and data signal lines 21, 22 are provided with a communication control circuit 11. A synchronization detection character by which the initial change point of the reception data signal line 22 is recognized is used to implement data reception in which the reception data signal line level is sampled. Timing information of the reception data signal line 22 obtained from the result is used for a base data of detecting the speed and a central processing unit 12 sets again the communication control circuit 11 to the start-stop synchronization communication operating mode at the detected communication speed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous communication system that communicates communication data in an asynchronous manner, and more particularly to a communication speed detection method for an asynchronous communication system that detects the communication speed of communication data.

0002

[Prior Art] Conventionally, this type of communication speed detection method includes:
A plurality of receiving circuits are arranged in parallel and are set to perform reception at the respective communication speeds to be detected, and when a character is received, the character is received by the plurality of receiving circuits, and which one is received. Some detected communication speed by determining whether the circuit received the correct data.

[0003] Furthermore, when a character is received, the period during which the level of the received data signal line is in a non-idle state is automatically measured using a counter or other means, and after the character reception is completed, communication is performed based on the measurement result. There was something that detected speed. This method assumes that only one character is counted at any communication speed, but since the communication speed is unknown, the end of character reception is the time equivalent to the transmission time of one character at the lowest speed to be detected. The decision was made based on the fact that the period had passed.

0004

However, in the method of arranging a plurality of receiving circuits as described above, the type of speed that can be detected is determined at the time of designing the receiving circuit to be arranged, and changes are
It's not easy. In addition, since a receiving circuit is required for each type of speed to be detected, it is not economical, and since it is necessary to determine the character to be detected in advance, there is a problem that it is limited to one type of character. .

Furthermore, in the method of measuring the level of the signal line, the end of character reception is determined when the time equivalent to the transmission time of one character has passed at the minimum speed to be detected, so the actual communication speed is Receiving multiple characters within the same time is not allowed, even if the speed is faster than the minimum speed.
As a result, the character reception interval is limited to one character reception or more at the lowest speed. For example, if the minimum speed to be detected is 50 [bps], the character length is 8 bits, and there are start and stop bits of 1 bit before and after it, the character reception interval is (1/50 )
×(8+1+1)=1/5(sec)=200(msec)
c) or higher; for example, when character transmission is controlled by a program, a delay loop (d
There is a problem in that special measures such as insertion of an elay loop are required. In addition, hardware such as a counter that measures the period of non-idle state must be provided separately from the communication control means, so the number of parts increases, especially in the case of communication equipment that must accommodate multiple lines. Problems include an increase in the number of semiconductor devices, an associated increase in manufacturing costs, and an increase in the mounting space.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a communication speed detection method in an asynchronous communication system that is highly economical and capable of performing speed detection with great flexibility. do.

[0007]

[Problems to be Solved by the Invention] The present invention provides an asynchronous communication system that performs data communication at a plurality of communication speeds with a predetermined communication target via a data signal line. synchronous communication operation mode;
A function for performing data communication by switching by a central processing unit between a character synchronous communication mode in which data is received by a clock signal of an arbitrary speed using a synchronization detection character that can recognize the first change point of the data signal line. and when receiving a speed detection character from the data signal line, the central processing unit sets the communication means to a character synchronous communication mode, and sets the communication means to a character synchronous communication mode so that the communication speed is at least higher than the communication speed to be detected. A synchronous mode reception is performed in which the signal waveform of the speed detection character is sampled by the clock signal, and the received data is processed in accordance with timing information of the data signal line obtained from the sampling result of the speed detection character recognized as received data. A communication speed detection method in an asynchronous communication system is provided, which detects a transmission speed of a speed detection character and resets the communication means to an asynchronous communication operation mode corresponding to the detected communication speed.

[0008]

[Operation] Utilizes the character synchronous communication operation mode that most communication control means such as general communication control LSIs have, and uses synchronization detection characters that can recognize the first change point of the data signal line. The speed detection characters are sampled by the synchronous mode reception, and the timing information of the data signal line obtained from the sampling is used as basic data for speed detection.

[0009] Therefore, by using the present invention, data signal lines can be sampled without adding hardware in many cases, and speed detection processing can be performed using timing information obtained by this sampling method. Therefore, economical and flexible communication speed detection can be realized.

0010

Embodiments Hereinafter, embodiments of the present invention will be explained based on the drawings of FIGS. 1 and 2. FIG. 1 is a block diagram showing a schematic configuration of an asynchronous data communication device using a communication speed detection method according to the present invention. In the figure, the communication control circuit (hereinafter referred to as "LSI") is a small and high-performance LSI for communication control. When designing such an LSI,
Microprocessor-controlled communication control LSIs called serial communication controllers or multi-protocol communication controllers are often used, and these devices are capable of character-synchronous communication using arbitrary characters as synchronization detection characters and true clock signals. It has operating modes. The LSI 11 according to the present embodiment also has a character synchronous communication operation mode in addition to the asynchronous communication operation mode, and the LSI 11 has an asynchronous communication operation mode and a character synchronous communication operation mode. It is set to the synchronous communication operation mode or the character synchronous communication operation mode, and performs data communication with a predetermined communication target via the transmission data signal line 21 and the reception data signal line 22, and also communicates with the predetermined communication target via the interrupt signal line 23 as necessary. and requests the CPU 12 to perform interrupt processing. Note that the clock signal for data transmission and reception is LSI1
1, and its speed can be controlled by the CPU 12. Furthermore, the length of one character in the character synchronous communication operation mode is 8 bits, and the synchronization detection character for detecting that synchronization has been established can be arbitrarily set by the CPU 12.

[0011] The CPU 12 connects to L via a data bus 24.
While controlling the operation of the SI 11, when an interrupt signal from the LSI 11 is input via the interrupt signal line 23, the interrupt request is accepted and predetermined interrupt processing is performed. That is, the CPU 12 has a 1-bit count reference value corresponding to each communication speed built-in in a predetermined table in advance, and the 1-bit length actual count value detected by the above-mentioned interrupt processing and each of the above-mentioned built-in count reference values. The communication speed is detected by comparing the .

The speed detection character that can be used in this embodiment is an ASCII code whose least significant bit has a value of "1", and FIG. 2 shows an example of the data communication character waveform. and a diagram of a sampling clock. Normally, the received data signal line 22 is at a high level, and characters are sequentially processed from the least significant bit (LSB) to the most significant bit (MSB) with a positive logic ( The logic value 1 is a high level). In this example, the character length is
Immediately after the 8-bit character, a high-level, 1-bit long stop bit is added. The character code in FIG. 2 is 0Dh in hexadecimal and corresponds to the carriage return (CR) character of the ASCII code.

Next, the communication speed detection operation in the asynchronous data communication apparatus shown in FIG. 1 will be explained. When detecting the communication speed, the CPU 12 first detects the LSI
11 to set the operation mode of the LSI 11 to the character synchronous communication operation mode. At this time, the reception clock is set to the data sampling clock (in the example, a clock that is four times the maximum communication speed of the character to be detected), and the synchronization detection character is set to the sampling value "1" after the consecutive sampling values "1". A character (7Fh in hexadecimal if the synchronization detection character is one character) is set such that synchronization is considered to be established upon occurrence of "0", and the reception operation is started.

When the LSI 11 enters the receiving state, it starts sampling the level of the received data signal line 22 using the set clock (see FIG. 2(b)). Here, if no character has been received yet, receive data signal line 2
2 is a high level, and the sampling value is always “1”
Therefore, the division value at any 8-bit boundary of the sampling data string is FFh in hexadecimal, so LS
I11 determines that synchronization has not yet been established. Then, when reception of a predetermined character begins and the reception data signal line 22 changes from high level to low level according to the start bit of the character (see FIG. 2(a)).
, the next sampling value becomes "0" for the first time. When the above sampling value becomes "0", the division value at the 8-bit boundary becomes 7Fh in hexadecimal, which matches the synchronization detection character, so the LSI 11 considers that synchronization has been established at this point, and from now on, the 8-bit Every time sampling for a minute is completed, an interrupt signal requesting to take over the sampling data is output to the CPU 12 via the interrupt signal line 24.

When the CPU 12 receives an interrupt request from the LSI 11, it reads the sampling result of the reception data signal line 22 as 8-bit reception data. Then, the CPU 12 reads the sampling results of the received data signal line 22 in chronological order (from the lower bit to the upper bit).
, and count how many consecutive bits have a bit value of “0”. This count indicates that the bit value is “
The process ends when a bit that is 1 appears, but if all bits in the result of one sampling are 0, the process waits for the next interrupt request and performs the same process.

In the embodiment, since the least significant bit of the character is "1", the period in which "0" level bits continue in the sampling result corresponds to the reception time of the start bit (1 in asynchronous communication). bit time). In other words, the bit time corresponding to the sum of the number of consecutive "0" bits in the sampling result and the number of "0" bits in the synchronization detection character (1 in the case of 7Fh in the embodiment) is
It is equal to 1 bit time of the communication speed to be detected. Therefore,
If the reference value of the "0" bit count is stored in the CPU 12 in advance, the communication speed can be detected by comparing it with the actual count value.

When the CPU 12 detects the communication speed, the CPU 12 resets the LSI 11 to the asynchronous communication operation mode corresponding to the detected speed, and can start asynchronous communication. Therefore, in this embodiment, in the character synchronous communication operation mode, the received data signal line level is sampled using a synchronization detection character that can recognize the first change point of the data signal line, so the conventional hardware is completely changed. It is possible to detect the speed of asynchronous communication without adding Furthermore, the range of characters that can be used for speed detection is wide, and changes in the speed to be detected can be handled simply by rewriting the table of count reference values referenced by the CPU 12. Furthermore, since the speed detection ends when the processing time of the LSI 11 and CPU 12 has elapsed from the end of the start bit, it is much earlier than in the conventional method, and the time interval between subsequent characters is limited. can be significantly alleviated.

[0018]

Effects of the Invention As explained above, the present invention is applicable to normal data communication in an asynchronous communication system that performs data communication at a plurality of communication speeds with a predetermined communication target via a data signal line. a start-stop synchronous communication mode in which the central processing unit and a communication control means having a function of performing data communication by switching the communication means, and when receiving speed detection characters from the data signal line, the central processing unit sets the communication means to a character synchronous communication mode. , performing synchronous mode reception in which the signal waveform of the speed detection character is sampled by the clock signal having a communication speed higher than or equal to at least the communication speed to be detected;
The transmission speed of the received speed detection character is detected in accordance with the timing information of the data signal line obtained from the sampling result of the speed detection character recognized as received data, and the communication means is controlled at the detected communication speed. Since the setting is reset to the start-stop synchronous communication operation mode, it is highly economical and
In addition, it is possible to perform speed detection with great flexibility.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an asynchronous data communication device using a communication speed detection method according to the present invention.

FIG. 2 is a diagram showing waveforms and sampling clocks of data communication characters in this embodiment.

[Explanation of symbols]

11 Communication control circuit (LSI) 12 Central processing unit (CPU) 21, 22 Data signal line 23 Interrupt signal line 24 Data bus

Claims (1)

[Claims] 1. An asynchronous communication system that performs data communication at a plurality of communication speeds with a predetermined communication target via a data signal line, comprising: an asynchronous communication operation mode for normal data communication; Equipped with a function to perform data communication by switching between a character synchronous communication mode in which data is received using a clock signal at an arbitrary speed using synchronization detection characters that can recognize the first change point of the data signal line, and a central processing unit. when receiving the speed detection characters from the data signal line, the central processing unit sets the communication means to a character synchronous communication mode, and when the speed detection characters are received from the data signal line, Synchronous mode reception is performed in which the signal waveform of the speed detection character is sampled by a clock signal, and the received speed is determined according to the timing information of the data signal line obtained from the sampling result of the speed detection character recognized as received data. A communication speed detection method in an asynchronous communication system, characterized in that the transmission speed of a detection character is detected, and the communication means is reset to an asynchronous communication operation mode corresponding to the detected communication speed.