JPS6315677B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory suitable for high-speed operation, and particularly to a complementary semiconductor memory having an N-channel field effect transistor and a P-channel field effect transistor. .

[Conventional technology]

In recent years, an N-channel metal oxide field effect transistor (hereinafter abbreviated as NMOS) and
A dynamic type memory using a memory cell consisting of a capacitor has been put into practical use, but this type of memory has a problem in that it takes a long time to read information from the memory cell onto a data line.

In other words, when a memory cell is selected, the capacitance terminal voltage increases due to the influence of the data line voltage, so for the NMOS in the memory cell, the source connected to this capacitance terminal and the word line The voltage between connected gates does not rise sharply even when the word line voltage increases. Therefore, since the conductance of the NMOS does not increase much, it takes a long time for the information in the memory cell to be completely read onto the data line. Therefore, it is necessary to delay the timing at which the subsequent detection amplifier starts operating, and it takes time before the information in the memory cell can be used externally.

This problem is related to P-channel MOS (hereinafter referred to as PMOS).
The same applies to (abbreviated as ).

[Purpose of the invention]

An object of the present invention is to provide a high-speed semiconductor memory that solves this conventional problem.

For this reason, in the present invention, when reading information in a memory cell, the NMOS or
Among the electrode regions of the PMOS, the electrode region connected to the data line is operated as a source.

[Embodiments of the invention]

The present invention will be explained below based on Examples.

FIG. 1 shows a first embodiment of the invention.

In the memory shown in FIG. 1, a pair of data lines D ₀ ,
D ₀ is connected to the preamplifier PA and crosses the data line D ₀ to the 64 memory cell selection word lines W ₀ ~
W ₆₃ and a word line W _D for dummy cell selection are provided, and 64 word lines ₀ to ₆₃ for memory cell selection and a word line _D for dummy cell selection are provided crossing the data line ₀ . . Memory cells MC are provided at the intersections of these word lines W ₀ to W ₆₃ , ₀ to ₆₃ and data lines D ₀ , ₀ , and memory cells MC are provided at the intersections of the dummy cell word lines W _D , _D and data lines D ₀ , ₀ . A dummy cell DMC is provided. The memory cell MC consists of a PMOSQ ₄ and a capacitance C ₄ connected to the drain of this PMOSQ ₄ .
The gate of PMOSQ ₄ is connected to the word line, and the source is connected to the data line. On the other hand, the dummy cell DMC consists of a PMOS Q ₆ , a capacitance C ₆ connected to the drain of this PMOS, and a PMOS Q ₈ that initializes the potential of this capacitance.

The NMOS and PMOS used in the embodiments of the present invention are all enhanced types. The memory shown in FIG. 1 is provided with, for example, 64 pairs of data lines.
Components other than the data line pair D ₀ , ₀ are not shown for simplicity. Each data line is connected to common data lines _DC , _C via _PMOSQ14 , ₁₄ .
When selecting a memory cell, decoder 20 selects line 2.
14 address signals input from 2 a ₀ , a ₁ ,...
...a ₆ , ₀ , ₁ , ... ₆ , the word line driver 10 selectively activates the word line connected to the memory cell to be selected, for example, the word line W ₀ , and also activates this selection. The data line to which the target memory cell is connected, for example, the data line that forms a pair with _D0 , for example, the word line _D for dummy cells that intersects with ₀ , is selectively driven. Here, address signals ₀ , ₁ , ... ₆ are complementary signals of address signals a ₀ , a ₁ , ... a ₆ , respectively.

FIG. 2 shows this decoder 20 and word lines W ₀ ,
Driver 10 ₀₁ for driving W ₁ and driver 10 _D for driving word line _D for dummy cells.
This shows the following. In the figure, among the decoders 20, a partial decoder 20A for selecting a pair of word lines W ₀ and W ₁ , a partial decoder 20B for selecting a dummy word line _D , and a partial decoder 20B for selecting a pair of word lines W 0 and W 1, and a partial Only a partial decoder 20C is shown for further selecting one of the word lines. Partial decoder for word lines for other memory cells and word lines for dummy cells
The partial decoder for W _D is not shown for simplicity. In this embodiment, partial decoders for memory cell word lines W ₀ to W ₆₃ and ₀ to ₆₃ are provided in common for two adjacent word lines. Its configuration is as follows: the illustrated partial decoder 2
It is the same as 0A, and only the input address signal is different.

In other words, each partial decoder has six _NMOSQ24 to which six address signals are respectively input.
Has Q ₂₉ . There are six input address signals: a ₁ or ₁ , a ₂ or ₂ , ... a ₆ or ₆ , and when these are all low level, the two word lines connected to this partial decoder are configured to be selected. For example, word lines W ₀ , W ₁
Address signals a ₁ , a ₂ , . . . a ₆ are input to the partial decoder 20A for selecting , as shown in the figure. On the other hand, for example, a partial decoder (not shown) for selecting word lines W ₂ and W ₃ (not shown) receives complementary signals of a ₁ such as ₁ , a ₂ , ... a ₆ . ₁ is entered.

A pair of word lines is first selected by each partial decoder, and one of the selected word lines is further connected to NMOSQ ₂₀ , ₂₀ in the partial decoder 20C.
is selected by the output lines 12A and 12B. In this way, one word line to be selected is driven. For this purpose, lines 12A, 12B are connected to a plurality of drivers for memory cells.

The partial decoder 20B has an NMOSQ ₃₂ to which only the address signal _a6 is input so as to select the dummy cell word line _D when the address signal _a6 is at a low level. Similarly, word line W _D
A partial decoder (not shown) for selecting
It is configured to select the dummy cell word line W _D when the address signal ₆ is at a low level.

The driver ₁₀₀₁ also includes a latch circuit 30, _NMOSQ48 , _Q54 connected to word lines _W0 , _W1, respectively, and _NMOSQ46 and _PMOSQ44 commonly connected to these NMOS. NMOSQ ₄₈ and Q ₅₄ are controlled by voltages on lines 12A and 12B. The other word lines _W3 to _W63 , ₀ to ₆₃ are also connected to the latch circuit 30,
It has NMOSQ ₄₆ , Q ₄₈ , Q ₅₄ , and PMOSQ ₄₄ . Driver _10D differs from driver ₁₀₀₁ only in that it does not include _NMOSQ48 and _Q54 . The same is true for driver _10D .

The operation of the circuits shown in FIGS. 1 and 2 will be explained below with reference to the time chart shown in FIG.

First _{, due} to _the high- _{level precharge} signal _{φ P} shown in _{FIG .} Voltage Vcc (5 volts)
Precharge to. Therefore, the high level of the signal φ _P is higher than the voltage Vcc, NMOSQ ₂ , ₂ , Q ₃ ,
The voltage is chosen to be higher by the threshold voltage of _Q3 .
Further, the precharge signal φ _P turns on the NMOSQ ₅₃ of the latch circuit 30 connected to each word line, and sets the gate of the PMOSQ ₅₀ and the drain of the PMOSQ ₅₂ to 0 volts. As a result, PMOSQ ₅₀ is turned on and Q ₅₂ is turned off.
As a result, each word line is precharged to voltage Vcc and latched to that potential. On the other hand, the inverted signal _P of the signal φ _P is the dummy cell precharge line
in the dummy cell DMC via DPL,
Turn on PMOSQ ₈ and store low voltage in capacitance C ₆ .

Further, the signal φ _P is transmitted to the decoder 20 (20A,
Turn on NMOSQ ₂₂ in B) and connect wires 12C, 12
D is precharged to the voltage Vcc, and the gates of the word line driving transistors _Q46 are respectively connected to the voltage Vcc.
pre-charge and keep these NMOS on. Furthermore, the signal φ _P is within the driver 10 ₀₁ .
Turn on NMOSQ ₄₀ and Q ₄₂ and connect wires 12A and 12B
Turn on NMOSQ ₄₈ and Q ₅₄ via . In this way, all word lines are connected to
NMOSQ ₄₆ , Q ₄₈ , and Q ₅₄ are all turned on. At this time, as shown in FIG. 3c, when the signal φ _P is at a high level, the word line drive signal _X is at a high level. Therefore, in this precharge state, all word lines are held at voltage Vcc. After this, the signals φ _P and _P are at low level and
Can be changed to a high level. In this way, the precharge ends.

Thereafter, the address signal is input to the decoder 20 as shown in FIG. 3b. Now, if this address signal is used to select word line W ₀ , then
Signals _a0 to _a6 are all at low level and address signals ₀ to ₆ are all at high level. Therefore, in the partial decoder 20A for the word line W ₀
NMOSQ ₂₄ to Q ₂₈ and Q ₂₉ all remain off. Therefore, the output line 12C of the partial decoder 20A
is kept at a high level, and Q ₄₆ connected to word lines W ₀ and W ₁ is kept on. Similarly, output line 12D of partial decoder 20B is also held high, and NMOSQ ₄₆ in driver _10D is also held on. In the partial decoder connected to another word line, at least one of the address signals input thereto has a high level, so this partial decoder is connected to the word line.
Outputs a low level signal that turns off NMOSQ ₄₆ . In this way, the signal _X is no longer applied to word lines other than word lines W ₀ , W ₁ , and _D. These word lines are connected to voltage Vcc by latch circuit 30.
will be maintained.

On the other hand, NMOSQ ₂₀ in the partial decoder 20C,
Q ₂₀ responds to the low level and high level address signals a ₀ and ₀ , respectively, and turns off and on, and the line 1
2A is held high, but line 12B is
Discharge to low level through NMOS ₂₀ . This results in NMOSQ ₄₈ in all drivers remaining on, but NMOSQ ₅₄ in all drivers turning off. In this way, word line W ₁ also receives signal _X
is no longer applied.

As is clear from the above description, the output of the partial decoder 20A maintains a high level only when the word line corresponding to that decoder is selected.
When not selected, the level changes from high to low.

Thus, only the selected word line W ₀ and the dummy word line _D remain connected to the signal _X.

Thereafter, when the signal _X is shifted to a low level as shown in FIG. 3c, the selected word line W ₀
The voltage φ _W0 is rapidly discharged to a low level via NMOS Q ₄₆ and Q ₄₈ in the driver 10 ₀₁ as shown in FIG. 3d. Selected dummy word line _D
The voltage φ _WD is also NMOSQ ₄₆ , Q ₄₈ in the driver 10 _D
discharge to low levels through.

During this discharge, the difference between the source electrode and gate voltage of NMOSQ ₄₆ and Q ₄₈ does not decrease during the discharge. Therefore, discharge occurs at high speed.

At this time, since the line 14 and the line 12c are capacitively coupled, when the signal _X shifts from a high level to a low level, the voltage of the output line 12C of the partial decoder 20A may fall below Vcc.
PMOSQ ₄₄ prevents this decline. i.e. PMOSQ ₄₄ for unselected word lines
remains off, but the selected word line
PMOSQ ₄₄ for W ₀ , _D turns on when φ _W0 , φ _WD goes low and connects lines 12C, 12D.
Continue to hold at Vcc. The lines 12A and 12B also cause a level drop due to the capacitance when the level of _X falls, but the amount of this drop is small because the capacitance of the lines 12A and 12B is large, so no PMOS is provided for _Q44 .

As a result of this word line W ₀ , _D discharge, φ _W0 , φ _WD
are, respectively, Vcc-|V _TH (Q ₄ )|, Vcc-|V _TH
(Q ₆ )｜When the following occurs, the memory cell MC
PMOSQ ₄ and PMOSQ ₆ in the dummy cell DMC are turned on. Here, V _TH (Q ₄ ) and V _TH (Q ₆ ) are threshold values of PMOSQ ₄ and Q ₆ , respectively. The following also shows the threshold value of NMOS or PMOS. As a result of _Q4 in memory cell MC being turned on,
The potential of the data line D ₀ decreases by a value corresponding to the voltage between the terminals of the capacitance C ₄ in the memory cell MC. This voltage between the terminals of the memory cell
It is set to Vcc or a low level depending on whether the information to be stored in the MC is "1" or "0". Therefore, as shown in FIG. 3e, the memory cell
When "1" is read from the memory cell MC, the potential of the data line _D0 remains almost at Vcc, but when "0" is read from the memory cell MC, the potential of the data line becomes somewhat lower than Vcc. The value will be lower. On the other hand, since 0 volt is stored in the capacitance in the dummy cell DMC at the time of precharging, when this dummy cell is read, the data line ₀
The potential of takes a value somewhat lower than Vcc. The capacitance C ₆ is configured to have approximately half the capacitance of the capacitance C ₄ so that the potential of the data line D ₀ is located between two possible values of the data line ₀ . The capacitances of C ₄ and C ₆ are
Since the capacitance of the data line D _0,0 is selected to be several tenths or several hundredths of _{the capacitance} , even if the voltage of the data line _D0,0 changes from Vcc, it will be a small change of several tens to hundreds of millivolts. It's just a value. Therefore, it can be considered that the voltage of the data lines D ₀ , ₀ remains approximately 5V.

During this time, when the signal φ _W0 continues to discharge toward 0 volts, the PMOSQ ₄ connected to the word line W ₀
The potential of the gate of and the source connected to the data line D ₀ increases further, the conductance of PMOSQ ₄ increases, and the conductivity of PMOSQ ₄ becomes better as the word line voltage φ _W0 decreases. Therefore, the information in the memory cell MC is read out to the data line _D0 at high speed as described above. Reading of information in dummy cell DMC to data line ₀ is similarly performed at high speed.

In this way, voltage changes on the data lines D ₀ , ₀ due to reading of memory cells and dummy cells are performed at high speed. The potential of this data line D ₀ , ₀ is
Differential amplification is performed by a flip-prop preamplifier PA consisting of NMOSQ ₁₀ , ₁₀ and PMOSQ ₁₀ ', ₁₀ '. That is, as shown in FIG. 3f, the signal φ _S
increases from a low level to a high level Vcc,
Turn on NMOSQ ₁₂ and activate preamplifier PA. As a result, depending on the magnitude of the voltage of the data lines D ₀ , ₀ , the NMOSQ ₁₀ , ₁₀ set and the PMOS
One of the pairs of Q ₁₀ ′ and Q ₁₀ ′ is on, and the other is off. For example, as shown in FIG. 3e, when the voltage on data line D ₀ is greater than the voltage on data line ₀ , NMOSQ ₁₀ and PMOS ₁₀ ' are turned off, and ₁₀ and Q ₁₀ ' are turned on. As a result, the voltage on data line ₀ rapidly discharges towards 0 volts, as shown in Figure 3e. The voltage on data line D ₀ does not change. After that, the signal _φy0 applied to the gates of _PMOSQ14 , ₁₄ corresponding to the memory cell MC to be read is changed from high level to low level,
When PMOSQ ₁₄ and ₁₄ are turned on, the common data line D _C maintains a high level, and the data line _C changes to a low level. The stored information of the memory cell read out can be known from the voltage changes of the data lines D _C and _C. After this read operation, all signals are returned to precharge signals as shown in FIG. The read operation is thus completed.

In order to store information in a memory cell in this memory, the information is read from the memory cell in which the information is to be written as described above, and then the signals involved in the read operation are returned to the precharge level. Before that, Vcc or a low level voltage is applied depending on whether the information to be written to the common data lines _DC , _C is "1" or "0", and by the action of the preamplifier PA,
After changing the voltage of the data line D ₀ , ₀ to either Vcc or a low level voltage depending on the information to be written, all the signals involved in the read operation are returned to the precharge level. In this way, the write operation ends.

FIG. 4 shows a second embodiment of the invention relating to a decoder and driver. In FIG. 4, the same reference numbers as in FIG. 2 indicate the same items. Decoder 20 has exactly the same configuration as the decoder shown in FIG. The driver is different from that shown in FIG. The driver 10 ₀₁ ′ for word lines W ₀ and W ₁ is
Output line 1 of decoder 20A via NMOSQ ₄₅
2C, NMOSQ ₄₇ , Q ₄₉ and signal _φ
Discharge the word line using The signal _φX is
At the timing when the signal _X shown in Figure 3 changes from high level to low level and from low level to high level, the signal These are signals that change in level (0 volts).

The word line and dummy word line are precharged to voltage Vcc by a latch circuit 30 having the same structure as the latch circuit 30 of FIG.

Output lines 12A, 12B, 12 of decoder 20
C and 12D are also precharged to Vcc. As a result, after precharging, _the gate voltage of Q ₄₇ in all drivers is
Discharged to Vcc−V _TH (Q ₄₅ ). Therefore,
NMOSQ ₄₇ is on when signal _φX is 0 volts, the gate voltage of NMOSQ ₄₉ is 0 volts, and NMOSQ ₄₉ is in the off state. on the other hand,
NMOSQ ₄₈ and Q ₅₄ are in the on state.

Then, in response to the address signal, the decoder 2
Once the output _of 0 is established, the partial decoders 20A, ₂ for the selected word line, e.g.
The output of the partial decoders other than 0B becomes ₀ volts, the NMOSQ ₄₅ in the driver connected to these partial decoders turns on, and the gate voltage of NMOSQ ₄₇ becomes The voltage is discharged to 0 volts through one or more of NMOSQ ₂₄ to Q ₂₉ in the on state.
As a result, connected to NMOSQ ₄₅ like this
NMOSQ ₄₇ is turned off. selected word line,
For example, NMOSQ ₄₇ for W ₀ and _D remains on.

On the other hand, the output lines 12A, 1 of the partial decoder 20C
Among the signal lines 2B, the voltages of the signal lines 12B that do not correspond to the word line W ₀ to be selected are reduced to 0 volts by the decoder 20C. Therefore, NMOSQ ₄₈ for word line W ₀ remains on, but word line
NMOSQ ₅₄ for W ₁ is turned off.

After _this decoder output _is determined, when _{the signal φ}
The gate voltage of becomes sufficiently higher than the original Vcc−V _TH (Q ₄₅ ), and NMOSQ ₄₅ in these drivers is turned off and NMOSQ ₄₇ is turned on. As a result, NMOSQ ₄₉ in these drivers is turned on.

Thus, only the selected word line W ₀ , _D is discharged to a low level (0 volts). The other word lines remain held at voltage Vcc by latch circuit 30.

As described above, the driver shown in FIG. 4 has the advantage that, unlike the driver shown in FIG. 3, the driver can be constructed entirely of NMOS.

Additionally, the selected word line does not need to be discharged through line 14, which is a long and therefore capacitive line.

Therefore, the word line is discharged faster than in FIG.

FIG. 5 shows a third embodiment of the invention. Fifth
Although only one pair of data lines D ₀ , ₀ is shown in the figure, in reality, a plurality of pairs of data lines are provided.

The memory shown in this figure is
As described in No. 4044340, a pair of data lines D ₀ ,
D ₀ are arranged close to each other and parallel to each other,
Another feature is that memory cells and dummy cells are arranged only at one of the two intersections between each word line and each data line pair.

In Figure 5, memory cell MC, dummy cell
Figures 1 and 2 show the first embodiment of the DMC, preamplifier PA, latch circuit 30, partial decoder 20A, etc.
Circuits with the same reference symbols as those shown in the figures are constructed of exactly the same components and operate in exactly the same way.

The circuit in FIG. 5 is different from the circuits in FIGS. 1 and 2 in that the partial decoder 20C' is the partial decoder 20C in FIG. 2 with NMOSQs ₂₁ and ₂₁ added. The decoder for selecting the point and dummy cell word lines W _D and _D consists of a partial decoder 20C′ and NMOSQ ₄₈ and Q ₅₄ ,
The dummy cell decoder 20B shown in FIG. 2 is not provided. The difference between the latter is that the dummy cell word lines W _D and _D are respectively address signals.
This means that it is selected when a ₀ and a ₀ are at low levels. Due to this difference, the selection operation of the dummy cell word line is not different from that of the memory shown in FIG. 2. In the memory shown in FIG. 5, the decoder can be simplified by selecting the dummy cell word line using address signals a ₀ , ₀ .

The difference between the former is the main circuit difference between the memory shown in FIG. 5 and the memories shown in FIGS. 1 and 2. This difference has the effect that when writing information into the memory cell MC, the low level voltage written into the memory cell MC can be made sufficiently low.

In FIG. 5, when writing information to a memory cell, precharging and decoding operations are performed in exactly the same way as in the memory shown in _FIG . Change. This change in word line voltage causes memory cell MC to be read out. The characteristic feature of this embodiment is that when the preamplifier PA is activated, the NMOSQ ₂₁ and ₂₁ are turned on by the signal φ _S for this purpose, and the voltages of the signal lines 12A and 12B are held at 0 volts. In this way, the NMOSQ ₄₈ connected to the word line W ₀ , which had been in the on state, is turned off, and the word line W ₀ is placed in a floating state.

On the other hand, due to the action of the activated preamplifier PA, one data line of all data line pairs
Vcc is held, while the other drops to 0 volts. Word line W ₀ is coupled to all data lines by stray _capacitance C _0,0 . Therefore, when half of all data lines drop to 0 volts, this capacitive coupling causes the voltage on word line W ₀ to drop to a negative voltage. However, the voltage of the word line W ₀ does not become lower than -V _TH (Q ₄₈ ). This is because when the voltage is lower than this, the NMOSQ ₄₈ turns on and current flows from the signal _X in the 0 volt state to the word line W ₀ .

In this state, data line D ₀ and word line W ₀
If ₀ volts were applied to the data line D ₀ in order to write information to _the memory cell MC at the intersection of _TH (Q ₄₈ ) and
It depends on the magnitude relationship of the threshold value V _TH (Q ₄ ) of PMOSQ ₄ in the memory cell. That is, +V _TH (Q ₄₈ ) < |
When V _TH (Q ₄ )|, 0 volts is written to the capacitance C ₄ in the memory cell. On the other hand, +
When V _TH (Q ₄₈ ) > |V _TH (Q ₄ )|, _a small positive voltage |V _TH (Q ₄ )|−V _TH
(Q ₄₈ ) | is written.

Therefore, in order to satisfy the former condition, V _TH (Q ₄ ),
For example, if V _TH (Q ₄₈ ) is determined, each −1.0
(V), 1.2 (V), the low level voltage written to the memory cell becomes 0 volts. Therefore, the voltage difference between the high level voltage and the low level voltage written to the memory cell is equal to Vcc (5 volts). In the memories of the first and second embodiments already described, the lowest voltage of the selected word line is 0 volts, so the low level voltage written to the capacitance of the memory cell is |V _TH (Q ₄ ) | is. Therefore, the voltage difference between the high level voltage and the low level voltage written to the memory cell is 4 volts. The memory shown in FIG. 5 can store a larger voltage difference, and is effective in speeding up reading, preventing malfunctions, and increasing refresh cycles.

The above is an example in which PMOS is used for the memory cell and NMOS is used for the peripheral circuit, but the present invention can also be realized using NMOS for the memory cell and PMOS for the peripheral circuit. That is, all NMOS in each of the above embodiments is replaced with PMOS,
All PMOSs are replaced with NMOSs, power supply voltage Vcc is applied to the places where the ground potential is applied, and ground potential is applied to the places where the power supply voltage Vcc is applied. A pulse that changes from a low level to a high level accompanying this is replaced with a pulse that changes from a high level to a low level. Therefore, in this fourth embodiment, the signals φ ₈ , ₈ , the address signal a _i , and the signals _X , φ _S are changed to signals showing level changes as shown in FIG. 6 a, b, c, and f, respectively. do. The operation of the memory configured in this way can be easily understood by referring to FIG. In this example, _the data lines D _0,0 are
It is precharged to a low level by the precharge signal _φP . The word line voltage is also precharged to a low voltage. Selected word line e.g.
The voltage φ _W0 , _WD of W ₀ , _D rises to a high level,
Read information from memory cells. As a result, the data line D ₀ remains at 0 volts, and after the data line ₀ changes to a voltage somewhat greater than 0 volts, it is raised to Vcc by the operation of the preamplifier.

In this memory as well, it is possible to increase the word line selection speed or the read speed of memory cells and dummy cells as seen in the first embodiment. The voltage between the gate and source of the PMOS for producing a voltage change on the selected word line does not change even when the word line voltage changes. Furthermore, when the voltage of the data line connected to the memory cell to be read changes based on the stored information of the memory cell to be read, the voltage within the memory cell changes.
This is because the voltage between the source and gate of the NMOS increases as the word line voltage rises.

FIG. 7 shows an example of the cross-sectional structure of the second embodiment of the present invention. An n-type well 52 with an impurity concentration of about 10 ¹⁵ cm ^-3 is formed in a region where memory cells are arranged on a P-type Si substrate 51 with a substrate specific resistance δ _sub = about 40 Ω·cm. In the memory cell portion on the surface of the substrate, a P ⁺ impurity layer 53 having a higher impurity concentration than the substrate,
54 is formed for the source and drain, and a gate 55 is made of a highly conductive material such as polycrystalline silicon, and a gate electrode 56 biased to the ground potential is formed, and a hole inversion layer is formed on the surface of the N-type well substrate. A plurality of one-transistor type memory cells are formed in which the capacitor formed between the capacitor 57 and the capacitor 57 serves as a storage electrode. Only one memory cell is shown in the figure. In this structure, the gate electrode 55 is connected to the word line 62 made of aluminum and the contact portion 50.
Connected at. Similarly, the P-type diffusion layer 53 constitutes a part of the data line made of the P-type diffusion layer. In the decoder and driver section on the surface of the P-type Si substrate on which the n-type well is not formed, the decoder and driver for driving word lines are made using NMOS. The figure shows a source 58, a drain 59, and a gate 6 formed of an n-type impurity layer.
One NMOS composed of 0 is illustrated.
The source 58 and the drain 59 are connected to word line low resistance electrode materials 61 and 62, such as aluminum, respectively, and the gate 63 is connected to the low resistance electrode material 61 and 62, respectively.
Connected to 3. In addition, in the n-type well 52,
During circuit operation, the electrode 64 and the n-type impurity layer 65
A voltage higher than Vcc generated by the circuit through V _W
is supplied, and when power is applied to the memory circuit, the Vcc electrode 66 and the shot diode 6 formed at the interface between this electrode 66 and the n-type well
7, the potential of the N-type well rises following the rise of the power supply voltage Vcc without delay. As a result, for example, the P ⁺ layer 53 of the pnp transistor formed by the diffusion layer 53, the well 52, and the substrate 51 is transferred to the n-type well 52.
This is caused by the ^potential rising more rapidly than the potential of
This prevents a large amount of current from flowing between the P ⁺ layer 53 and the P substrate 51. Also, during memory operation,
By making V _W sufficiently larger than Vcc, the above
Prevents the PNP transistor from becoming forward biased. Note that 68 is an interlayer insulating film;
9 is an oxide isolation region. Further, -3 volts is applied to the substrate 51. Note that the voltage V _W is generated by the circuit shown in FIG. Oscillator 8
From 0, pulses whose low level and high level are 0 volts and Vcc volts, respectively, are repeatedly output and input to a rectifier circuit consisting of capacitances C ₆₀ , NMOSQ ₆₀ , and Q ₆₁ . Rectifier circuit NMOSQ ₆₁
Vcc is applied to the drain of.
The voltage V _W output from the source of NMOSQ ₆₀ is V _W = 2Vcc - V _TH (Q ₆₀ ) - V _TH (Q ₆₁ ), and can be made sufficiently larger than Vcc.

In the structure shown in FIG. 7, the impurity diffusion layers 53 and 54 for the source and drain of the memory cell portion are not provided, and the impurity diffusion layers 53 and 54 are formed so as to penetrate through the insulating film 68 on top of these 53 and reach the surface portion of the substrate 51. By providing a metal electrode insulated from the word line 62, forming a Schottky diode between this electrode and the substrate 51, and connecting the metal electrode of the Schottky diode to the data line, the diffusion layer 53 and 54, the manufacturing process can be shortened by one step.

Furthermore, when the PMOSQ ₄₄ is provided in the driver 10 as in the first and third embodiments, this
PMOSQ ₄₄ is clearly located within N-well 52 of FIG.

It is also effective to use a junction field effect transistor or a Schottky gate field effect transistor instead of the metal oxide field effect transistor used in the above embodiments.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to speed up the selection of word lines and read out memory information, and as a result, a high-speed memory can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of a first embodiment of the present invention, and FIG. 2 shows a decoder in the first embodiment,
A detailed circuit diagram of the driver, FIG. 3 is a signal time chart for explaining the operation of the memory of the first embodiment, and FIG. 4 is a circuit diagram of the driver and decoder according to the second embodiment of the present invention. , FIG. 5 is a circuit diagram of the third embodiment of the present invention, FIG. 6 is a time chart of signals for explaining the operation of the memory in the fourth embodiment of the present invention, and FIG. 7 is a circuit diagram of the third embodiment of the present invention. FIG. 8, a diagram illustrating a cross-sectional structure of a memory according to a second embodiment of the present invention, is a diagram of a well bias voltage generation circuit used in the memory of FIG. 7. _D0 , ₀ ...data line, _W0 to _W63 , ₀ to ₆₃ ...word line for memory cell, W _D , _D ...word line for dummy cell, MC...memory cell, DMC...dummy cell,
10, 10 ₀₁ , 10 ₀₁ , 10 _D , 10' _D ...driver, 20, 20A, 20B, 20C... decoder.

Claims (1)

[Claims] 1. A plurality of data lines, a plurality of word lines provided to intersect the plurality of data lines, a memory cell provided at the intersection of the plurality of data lines and the word line, and a memory cell. means for setting a data line voltage to which a memory cell to be selected is connected to a predetermined first voltage when selecting a cell; and means for setting a word line voltage to which a memory cell to be selected is connected to a predetermined first voltage when selecting a memory cell;
and a word line driver for changing a predetermined non-selection voltage to a selection voltage, and the memory cell has a first region connected to a data line, a gate electrode connected to the word line, and a storage information a field-effect transistor having a second region connected to a terminal having a predetermined second voltage according to the memory cell; In the semiconductor memory, the voltage of the data line is changed according to the voltage of the data line, and the first voltage setting means and the terminal having the second voltage are configured to
each region includes means for outputting a voltage for operating as a source and a drain,
The driver applies a non-selection voltage to a word line other than the word line to which the memory cell to be selected is connected, the difference from the first voltage not exceeding the threshold of the transistor, and Means for applying selection voltages whose difference from the first voltage exceeds the threshold of the transistor to the word lines connected to the memory cells, and before selecting the memory cells, all the word lines are connected in advance. In a semiconductor memory comprising means for setting the non-selection voltage, and means for setting the voltage of a word line to which a memory cell to be selected is connected to the selection voltage when selecting a memory cell, the voltage setting means ,
Provided for each pair of adjacent word lines, these are connected to the selection voltage, and a setting field effect transistor for voltage setting is connected to each of the setting field effect transistor and the pair of word lines. 1. A semiconductor memory comprising: a connection field-effect transistor for setting a word line to be selected; and means for turning on the setting field-effect transistor and the connection field-effect transistor connected to a word line to be selected. 2. In the semiconductor memory according to claim 1, the data line is composed of a plurality of data line pairs arranged close to each other in parallel, and the memory cell is arranged between each pair of data lines and the word line. A semiconductor characterized in that it is provided at one of two intersections with each of the word lines, and is provided with means for applying the selection voltage to the gate of the connection field-effect transistor after selecting the word line. memory. 3. The semiconductor memory according to claim 1, which has a semiconductor substrate having a first conductivity type and a well region having a second conductivity type provided in the substrate, and the memory cell has a semiconductor substrate having a first conductivity type. A semiconductor memory characterized by being provided within a well region. 4. In the semiconductor memory according to claim 3, the means for applying a predetermined bias voltage to the well region reverse biases a PN junction formed by the second region of the field effect transistor and the well. A semiconductor memory characterized in that it is a means for applying a sufficiently large voltage under certain conditions. 5. The semiconductor memory according to claim 4 includes a Schottky diode comprising the above-mentioned well region and a metal electrode provided in contact with the well region, wherein the metal electrode includes the above-mentioned Second
A semiconductor memory characterized in that a voltage of: