JPS6316656A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6316656A JPS6316656A JP61161124A JP16112486A JPS6316656A JP S6316656 A JPS6316656 A JP S6316656A JP 61161124 A JP61161124 A JP 61161124A JP 16112486 A JP16112486 A JP 16112486A JP S6316656 A JPS6316656 A JP S6316656A
- Authority
- JP
- Japan
- Prior art keywords
- region
- forming
- film
- semiconductor device
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
- H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に電界効果1
〜ランジスタとバイポーラトランジスタとを有する集積
回路を含む半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device.
-Relates to a method of manufacturing a semiconductor device including an integrated circuit having a transistor and a bipolar transistor.
〔従来の技術1
最近、半導体装置の応用範囲が広がるにつれて、電界効
果トランジスタとバイポーラトランジスタとの両者を含
むいわゆるBiMO3集積回路製品の種類も増え一般的
なものとなって来た、□しかし、従来、バイポーラトラ
ンジスタを回路素子一部として含むBiMO3集積回路
例えばBicMOs集積回路においては、CMO3装置
の製造工程内に新らたにバイポーラトランジスタ製造用
の工程を追加する事により製造するが、又はCMO3装
置製造中に形成される寄生バイポーラトランジスタを利
用していた。[Conventional technology 1] Recently, as the range of applications of semiconductor devices has expanded, the variety of so-called BiMO3 integrated circuit products, which include both field-effect transistors and bipolar transistors, has increased and become common. BiMO3 integrated circuits that include bipolar transistors as part of circuit elements, for example, BicMOS integrated circuits, are manufactured by adding a new process for manufacturing bipolar transistors to the manufacturing process of CMO3 devices, or by adding a new process for manufacturing bipolar transistors to the manufacturing process of CMO3 devices. It utilized a parasitic bipolar transistor formed inside.
上述した従来の半導体装置の製造方法は、例えばCM
OS装置の製造過程で共に形成される寄生のバイポーラ
トランジスタを構成素子として回路内に取込むには、寄
生のバイポーラトランジスタの電気的特性の制御が困難
である為、再現性が悪いという欠点があり、又バイポー
ラトランジスタ形成用のマスク工程を別に追加して形成
する製造方法の場合は、再現性は改善されるが製造工程
が長くなるという欠点がある。The conventional semiconductor device manufacturing method described above is, for example, CM
Incorporating parasitic bipolar transistors, which are formed together in the manufacturing process of an OS device, into a circuit as a component has the disadvantage of poor reproducibility because it is difficult to control the electrical characteristics of the parasitic bipolar transistors. In addition, in the case of a manufacturing method in which a mask process for forming a bipolar transistor is separately added, reproducibility is improved, but there is a drawback that the manufacturing process becomes longer.
本発明の目的は、製造工程を増加せずに再現性良くバイ
ポーラトランジスタを電界効果トランジスタを含む回路
素子と共に同時に製造出来る半導体装置の製造方法を提
供することにある。An object of the present invention is to provide a method for manufacturing a semiconductor device that can simultaneously manufacture bipolar transistors and circuit elements including field effect transistors with good reproducibility without increasing the number of manufacturing steps.
本発明の半導体装置の製造方法は、−導電型の半導体基
板に反対導電型のウェルを形成する工程と、前記ウェル
内に一導電型のベース領域を形成すると同時に前記ウェ
ル以外の前記半導体基板に一導電型の反転防止領域を形
成する工程と、前記ウェル及び前記反転防止領域以外の
前記半導体基板に反対導電型のソース領域及びドレイン
領域を形成すると同時に前記ベース領域内に反対導電型
のエミ・・ツタ領域を形成する工程とを含んで構成され
る。The method for manufacturing a semiconductor device of the present invention includes the steps of forming a well of an opposite conductivity type in a semiconductor substrate of a -conductivity type, and forming a base region of one conductivity type in the well, and simultaneously forming a base region of one conductivity type in the semiconductor substrate other than the well. Forming an inversion prevention region of one conductivity type, forming a source region and a drain region of opposite conductivity type in the semiconductor substrate other than the well and the inversion prevention region, and simultaneously forming an emitter region of the opposite conductivity type in the base region. - A step of forming an ivy region.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図(a)〜(c)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。FIGS. 1(a) to 1(c) are cross-sectional views of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention.
第1図(a>に示すように、Nウェル2a、2bを形成
したP型シリコン基板1に反転防止領域形成用のレジス
ト膜5a〜5Cを、窒化膜3a〜3C及びレジス1〜膜
4a〜4Cを形成した後、所定の形に形成する。As shown in FIG. 1(a), resist films 5a to 5C for forming an anti-inversion region are formed on a P-type silicon substrate 1 on which N wells 2a and 2b are formed, and nitride films 3a to 3C and resists 1 to 4a to After forming 4C, it is formed into a predetermined shape.
次に、第1図(b)に示すように、反転防止領域形成用
のレジストIt!5aをマスクとしてベース領域形成の
為窒化膜3a上のレジスト膜4aの一部を除去すると共
に1、更にP型不純物をイオン注入してベース領域とな
るP+層6と反転防止領域7を形成する。Next, as shown in FIG. 1(b), a resist It! for forming an inversion prevention region is applied. Using 5a as a mask, a part of the resist film 4a on the nitride film 3a is removed to form a base region, and 1 and P-type impurities are ion-implanted to form a P+ layer 6 that will become a base region and an inversion prevention region 7. .
その後、第1図(C>に示すように、レジスト膜5a〜
5c及びレジスl−膜4a〜4Cを除去して、LOGO
3酸化を行いフィールド領域上の酸化膜10を形成し、
次に所定の拡散領域上にN゛型のエミッタ領域8a、コ
レクタ領域のコンタクト部8d並びにNMO3のソース
領域8b及びドレイン領域8Cを形成した後に、更に、
Nウェル2b内にPMO3も形成し、この実施例を説明
するためのB1CMOS集積回路が出来る。Thereafter, as shown in FIG.
5c and the resist l-films 4a to 4C are removed, and the LOGO
3 oxidation is performed to form an oxide film 10 on the field region,
Next, after forming an N-type emitter region 8a, a collector region contact portion 8d, and an NMO3 source region 8b and drain region 8C on a predetermined diffusion region, further,
A PMO3 is also formed in the N-well 2b to form a B1CMOS integrated circuit for explaining this embodiment.
ここで、レジスト膜5a〜5Cの厚さはレジスト膜4a
〜4Cより十分厚いものを使う必要がある。Here, the thickness of the resist films 5a to 5C is the thickness of the resist film 4a.
It is necessary to use something sufficiently thicker than ~4C.
又、両方のレジスト膜4a〜4C及び5a〜5Cは、特
性が同じ材質でも異なっても良い。Further, both resist films 4a to 4C and 5a to 5C may be made of the same material or may have different characteristics.
以上説明したように本発明は、電界効果トランジスタと
バイポーラトランジスタを含む半導体装置のバイポーラ
トランジスタをウェル内に形成することによって電界効
果トランジスタの工程に特別の工程を追加せずにバイポ
ーラトランジスタを再現性良く製造できるという効果が
ある。As explained above, the present invention enables bipolar transistors to be manufactured with good reproducibility without adding any special process to the field effect transistor process by forming the bipolar transistor of a semiconductor device including a field effect transistor and a bipolar transistor in a well. It has the advantage of being manufacturable.
更に又、本発明は、反転防止領域形成用のイオン注入に
よって、ウェル内にベース領域を形成するのでベース領
域を十分薄くする事ができ、電流増幅率の高いバイポー
ラトランジスタを得ることができるという効果もある。Furthermore, the present invention has the effect that since the base region is formed in the well by ion implantation for forming the inversion prevention region, the base region can be made sufficiently thin, and a bipolar transistor with a high current amplification factor can be obtained. There is also.
第1図(a)〜(c)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。
1・・・P型シリコン基板、2a、2b・・・Nウェル
、3a、3b、3cm窒化膜、4a、4b、4c、5a
、5b、5c・・・レジスト膜、6・・・ベース領域、
7・・・反転防止領域、8a・・・エミッタ領域、8b
・・・ソース領域、8C・・・ドレイン領域、8d・・
・コンタクト領域、9a・・・ソース領域、9b・・・
ドレイン領域、10・・・酸化膜、1]、a、llb・
・・ゲート電極。FIGS. 1(a) to 1(c) are cross-sectional views of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention. 1...P type silicon substrate, 2a, 2b...N well, 3a, 3b, 3cm nitride film, 4a, 4b, 4c, 5a
, 5b, 5c... resist film, 6... base region,
7... Inversion prevention region, 8a... Emitter region, 8b
...Source region, 8C...Drain region, 8d...
- Contact region, 9a... Source region, 9b...
Drain region, 10... Oxide film, 1], a, llb.
...Gate electrode.
Claims (1)
工程と、前記ウェル内に一導電型のベース領域を形成す
ると同時に前記ウェル以外の前記半導体基板に一導電型
の反転防止領域を形成する工程と、前記ウェル及び前記
反転防止領域以外の前記半導体基板に反対導電型のソー
ス領域及びドレイン領域を形成すると同時に前記ベース
領域内に反対導電型のエミッタ領域を形成する工程とを
含むことを特徴とする半導体装置の製造方法。forming a well of an opposite conductivity type in a semiconductor substrate of one conductivity type, forming a base region of one conductivity type in the well, and at the same time forming an inversion prevention region of one conductivity type in the semiconductor substrate other than the well; forming a source region and a drain region of opposite conductivity type in the semiconductor substrate other than the well and the inversion prevention region, and simultaneously forming an emitter region of opposite conductivity type in the base region. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61161124A JPS6316656A (en) | 1986-07-08 | 1986-07-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61161124A JPS6316656A (en) | 1986-07-08 | 1986-07-08 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6316656A true JPS6316656A (en) | 1988-01-23 |
Family
ID=15729059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61161124A Pending JPS6316656A (en) | 1986-07-08 | 1986-07-08 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6316656A (en) |
-
1986
- 1986-07-08 JP JP61161124A patent/JPS6316656A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0196757B1 (en) | Semiconductor device comprising a bipolar transistor and a mos transistor and method of manufacturing the same | |
| EP0239216A2 (en) | CMOS compatible bipolar transistor | |
| JP2886186B2 (en) | Semiconductor device | |
| JPH0492416A (en) | Manufacture of semiconductor device | |
| JP2610906B2 (en) | Method for manufacturing BiMOS semiconductor circuit device | |
| JPH056961A (en) | Manufacture of semiconductor device | |
| JP3226252B2 (en) | Method for manufacturing semiconductor device | |
| JPH02241057A (en) | Manufacture of semiconductor integrated circuit | |
| JPH03155156A (en) | Manufacture of semiconductor device | |
| JPH04139766A (en) | Vertical type mos field effect transistor and its manufacture | |
| JPH02226759A (en) | Manufacture of bicmos type semiconductor integrated circuit | |
| JPH05102466A (en) | Mos type semiconductor device and manufacture thereof | |
| JPH05129535A (en) | Semiconductor integrated circuit and manufacture thereof | |
| JPH04346263A (en) | Manufacture of bi-cmos semiconductor device | |
| JPH0282569A (en) | Semiconductor device and its manufacture | |
| JPH0387058A (en) | Manufacturing method of semiconductor integrated circuit | |
| JPS6337642A (en) | Semiconductor integrated circuit device | |
| IE57376B1 (en) | Semiconductor devices | |
| JPH0346372A (en) | Mos type transistor | |
| JPH01117362A (en) | Manufacture of semiconductor integrated circuit device | |
| JPH0360150A (en) | Semiconductor device and its manufacture | |
| KR950021717A (en) | Manufacturing method of high voltage semiconductor device | |
| JPH06125044A (en) | Manufacture of semiconductor device | |
| JPH0621366A (en) | Method for manufacturing semiconductor device | |
| JPS63278371A (en) | Manufacture of bipolar transistor |