JPS63178331A - Data testing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (II) The present invention is a data test device, which simultaneously holds data supplied to a tagged data register in a test register of a test means, and tests the held data. By generating tags, faster processing is possible.

FIELD OF INDUSTRIAL APPLICATION] The present invention relates to a data testing device, and relates to a data testing device that tests incoming data to obtain a tag indicating the content of the data, and stores this tag in correspondence with the incoming data. Regarding.

When performing operations on floating point data, the contents of the floating point data being operated on are non-numbers and infinite.

It tests whether it is a zero or denormalized number, represents a non-number, infinity, etc. with a code called a tag, and processes floating-point data according to the tag.

[Conventional technology]

Conventionally, multiple pieces of floating point data supplied from a CPU to an arithmetic unit are sequentially written into a data storage section of a tag reading register, and a single floating point data is read out from this data section and sent to a test circuit. The tag generated by the test circuit is stored in the tag storage section of the tagged register.

[Problem that the invention seeks to solve]

In the conventional device described above, floating point data must be read from the tagged register and the generated tag must be written to the tagged register. The problem is that the tagged register must be accessed three times for each data, and the processing speed becomes slower as the number of accesses increases.

The present invention has been made in view of the above points, and an object of the present invention is to provide a data test device with high processing speed.

[Means for solving problems]

The data test device of the present invention includes a data storage section (11a)
It has a test register (24) that simultaneously holds data supplied to and stored in the test register (24).
) is provided with a test means (12) for supplying a tag obtained by testing the data held in the tag storage section (11b).

[Function] In the present invention, since data from the outside is stored in the data storage unit and simultaneously held in the test register, there is no need to read data from the data storage unit during testing, and tagged data The number of register accesses is reduced.

(Embodiment) FIG. 1 shows a block system diagram of an embodiment of the apparatus of the present invention.

In the figure, a terminal 10 is connected to a CPLI (not shown) via a bus interface circuit (not shown), and, for example, floating point data input from the CPU to the terminal 10 is transferred to a tagged data register 11 and a test register. is supplied to circuit 12. Tagged data register is data storage part 1
1a and a tag storage section 11b. Data storage section 11a.

The number of data stored in each tag storage section 11b and the number of tags are the same and correspond to each other on a one-to-one basis. The data from the terminal 10 described above is stored at a designated location in the data storage section 11a.

The test circuit 12 has the configuration shown in FIG. In the figure, floating point data such as 15-bit exponent data and 64-bit mantissa data are input in parallel to the terminal 20.
A control signal is input to the terminal 21, and a clock signal is input to the terminal 22.

When the write controller 23 is supplied with the data write control signal, it supplies exponent data and mantissa data to the test temporary register 24 in synchronization with the clock signal. Since the above data write control signal is also a write control signal to the data storage section 11a shown in the first diagram, the terminal 1
The floating point data input from 0 is written to the data storage section 11a and simultaneously written to the test temporary register 24 and held there.

Among the floating point data held in the test temporary register 24, exponent data is supplied to the total 911 test circuit 25 and the zero test circuit 26, respectively.

All 717 test circuits 25 have exponent data of all bits 117
The test result is supplied to the tag generation circuit 27. Further, the zero test circuit 26 tests whether the value of the exponent data is zero or not, and supplies the test result to the tag generation circuit 27.

Furthermore, among the floating point data written in the test temporary register 24, the MSB of the mantissa data is zero in the test circuit 28.
The mantissa data other than MS8 is supplied to the zero test circuit 2.
9. The zero test circuit 29 tests whether the value of the mantissa data other than the MSB is zero, and supplies the test result to the zero test circuit 28 and other circuits not shown in FIG. The zero test circuit 28 is an MS of mantissa data.
Based on the test results of the B and zero dest circuits 29, it is tested whether the value of the mantissa data is zero or not, and the test results are supplied to the tag generation circuit 27.

According to the test results of the above-mentioned all v1v test circuit 25 and zero test circuits 26, 28, and 29, the tag generation circuit 27 has floating point data of non-number and infinity.

A tag as a code indicating that the number is zero, a denormalized number, etc. is generated. This tag is provided to the read controller 30.

When the read controller 30 is supplied with the tag read control signal and the clock signal from the terminals 21 and 22, it reads the tag from the tag generation circuit 27 and outputs it from the read terminal 31 in synchronization with the clock signal. The tag output from the terminal 31 is supplied to and written into the tag storage section 11b of the tagged data register 11 shown in the first diagram.

In this way, data supplied from the outside is stored in the data storage section 11a and simultaneously held in the test temporary register 24 in the test circuit 12, so there is no need to read data from the data storage section 11a during testing. The number of times the tagged data register 11 is accessed is reduced, and processing can be performed at a correspondingly high speed.

〔Effect of the invention〕

As described above, the data storage device of the present invention can speed up tag generation processing, and is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the apparatus of the present invention, and FIG. 2 is a block diagram of an embodiment of the test circuit shown in FIG. In the figure, 11 is a tagged data register, 2 is a test circuit, 24 is a test temporary register, 25 is a total 717 test circuit, 26, 28, 29 is a zero test circuit, and 27 is a tag generation circuit.

Claims (1)

[Claims] Data supplied from the outside and stored in the data storage section (11a) of the tagged data register (11) is tested, a tag indicating the content of the data is generated, and the data register (11) is tested. 11) The data test device stores the data in the tag storage section (11b) in correspondence with the data, which includes a test register (24) that simultaneously holds the data supplied to and stored in the data storage section (11a). death,
A data test device comprising a test means (12) for testing data held in the test register (24) and supplying a tag obtained to the tag storage section (11b).