JPS6318656A - Resistor for semiconductor integrated circuit - Google Patents

Resistor for semiconductor integrated circuit

Info

Publication number
JPS6318656A
JPS6318656A JP16303386A JP16303386A JPS6318656A JP S6318656 A JPS6318656 A JP S6318656A JP 16303386 A JP16303386 A JP 16303386A JP 16303386 A JP16303386 A JP 16303386A JP S6318656 A JPS6318656 A JP S6318656A
Authority
JP
Japan
Prior art keywords
insulating film
silicon film
film
electrode
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16303386A
Other languages
Japanese (ja)
Inventor
Reiko Muto
武藤 玲子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16303386A priority Critical patent/JPS6318656A/en
Publication of JPS6318656A publication Critical patent/JPS6318656A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To implement high density in layout, by providing two opening parts in a silicon film so that a specified distance is provided from the periphery of the silicon film in an insulating film, which covers the silicon film, and connecting the silicon film and an electrode on an insulating film. CONSTITUTION:An insulating film 3 is attached so as to cover a silicon film 2, which is selectively formed on an insulating film 1. The entire silicon film 2 other than contact windows is covered with the insulating film 3. The silicon film 2 and electrodes 4 on the insulating film 3 are connected. Thus, the overlapped part is made to correspond to the positioning margin of the insulating film and the electrodes in only one process. High density can be implemented in this layout, and high density interconnection can be also implemented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路装置に関し特に絶縁膜上に形成
した高精度なシリコン被膜抵抗に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a highly accurate silicon film resistor formed on an insulating film.

〔従来の技術〕[Conventional technology]

従来、絶縁膜上に形成したシリコン被膜抵抗は第3図及
び第4図に示す構造となっていた。
Conventionally, a silicon film resistor formed on an insulating film has a structure shown in FIGS. 3 and 4.

第3図はその平面図、第4図はその断面図である。図に
おいて1は絶縁膜、2は一導電型のシリコン被膜で例え
ばポリンリコン、3はシリコン被膜の表面に成長させた
絶縁膜、4は電極で絶縁膜3をバターニングしてシリコ
ン被膜の両端を露出したコンタクト部によりシリコン被
膜と接続している。
FIG. 3 is a plan view thereof, and FIG. 4 is a sectional view thereof. In the figure, 1 is an insulating film, 2 is a silicon film of one conductivity type, such as polyrecon, 3 is an insulating film grown on the surface of the silicon film, 4 is an electrode, and the insulating film 3 is buttered to expose both ends of the silicon film. It is connected to the silicon film through the contact portion.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の抵抗は電極4がシリコン被膜2の両端を
被うように形成されているため、電極幅は抵抗幅に加え
、シリコン被膜2と電極4とのオーバーラツプ分が必要
である。このオーバーラツプは、バターニングの精度及
びシリコン被膜に対する電極工程の位置合わせのマージ
ンで、通常2μ程度であるので、例えば抵抗幅6μの場
合、電極幅は6+2X2= 10μとなる。このため、
抵抗間隔はシリコン被膜間隔でなく電極間隔により決定
される。例えば、抵抗間隔及び電極間隔を2μとすると
、抵抗部は8μピツチであるが、電極部は12μピツチ
となり、抵抗間隔を必要以上に離さなければならなく、
高密度なレイアウトができないという欠点がある。また
、配線幅も通常4〜6μ程度であるが、上記従来例では
抵抗電極部の幅は10μある為、配線の高密度化につい
ても問題があった。
In the conventional resistor described above, the electrode 4 is formed so as to cover both ends of the silicon film 2, so that the electrode width needs to include the overlap between the silicon film 2 and the electrode 4 in addition to the resistance width. This overlap is usually about 2μ due to the precision of patterning and the margin of positioning of the electrode process with respect to the silicon film, so for example, if the resistance width is 6μ, the electrode width will be 6+2X2=10μ. For this reason,
The resistance spacing is determined by the electrode spacing, not the silicon coating spacing. For example, if the resistor spacing and electrode spacing are 2μ, the resistor part has a pitch of 8μ, but the electrode part has a pitch of 12μ, which means that the resistor spacing must be made wider than necessary.
The drawback is that a high-density layout cannot be achieved. Furthermore, the width of the wiring is usually about 4 to 6 μm, but in the conventional example described above, the width of the resistive electrode portion is 10 μm, so there is also a problem in increasing the density of the wiring.

〔問題点を解決するための手段] 本発明は抵抗の電極幅を小さくすることによりレイアウ
トの高密度化を図ることを目的としている。すなわち、
本発明の要旨は絶縁膜によりシリコン被膜を被い、絶縁
膜のうちシリコン被膜上においてシリコン被膜の周縁か
ら所定の距離をおいた少なくとも2つの開口部を何し、
シリコン被膜と絶縁膜上の電極とを接続することを特徴
とした半導体集積回路用抵抗である。
[Means for Solving the Problems] The present invention aims to increase the density of the layout by reducing the electrode width of the resistor. That is,
The gist of the present invention is to cover a silicon film with an insulating film, and to form at least two openings on the silicon film in the insulating film at a predetermined distance from the periphery of the silicon film,
This is a resistor for a semiconductor integrated circuit characterized by connecting a silicon film and an electrode on an insulating film.

〔実施例1 次に本発明について図面を参照して説明する第1図は本
発明の一実施例の平面図、又第2図はそれを構成するパ
ターンの平面図である。
[Embodiment 1] Next, the present invention will be explained with reference to the drawings. Fig. 1 is a plan view of an embodiment of the present invention, and Fig. 2 is a plan view of a pattern constituting the same.

図において、1は絶縁膜、2はシリコン被膜、3は絶縁
膜、4は電極である。従来と異なるところはフンタクト
窓を除きシリコン被膜2のすべてを絶縁膜3で被うこと
である。
In the figure, 1 is an insulating film, 2 is a silicon coating, 3 is an insulating film, and 4 is an electrode. The difference from the conventional method is that the silicon coating 2 is entirely covered with an insulating film 3 except for the contact window.

〔発明の効果〕〔Effect of the invention〕

このように、絶縁膜1でシリコン被膜2の周縁を被うこ
とにより、電極幅はコンタクト窓の幅とコンタクト窓と
電極4とのオーバーラツプ分のみで良くなる。オーバー
ラツプは従来のシリコン被膜と、電極とのオーバーラツ
プがシリコン被膜と絶縁膜、絶縁膜と電極という2工程
にわたる位置合わせのマージンを必要としていたのに対
し、本発明では絶縁膜と電極という1工程の位置合わせ
のマージンですむので、従来の半分の1μで良い。従っ
てコンタクト窓を4μ口とすれば電極幅は6μとなる。
By covering the periphery of the silicon film 2 with the insulating film 1 in this manner, the electrode width is reduced to only the width of the contact window and the overlap between the contact window and the electrode 4. The overlap between the conventional silicon film and the electrode required a margin for positioning in two steps: the silicon film and the insulating film, and the insulating film and the electrode. Since it only requires a margin for positioning, 1μ, which is half of the conventional one, is enough. Therefore, if the contact window is 4μ, the electrode width will be 6μ.

この為例えば抵抗間隔及び電極間隔を2μとすると、抵
抗は従来12μピツチのところ8μピツチで設計でき、
レイアウトの高密度化が可能である。また、配線に関し
ても本発明により電極部の幅が従来10μのところ6μ
となったため、配線の高密度化も可能となった。
For this reason, for example, if the resistor spacing and electrode spacing are 2μ, the resistors can be designed with an 8μ pitch instead of the conventional 12μ pitch.
It is possible to increase the density of the layout. In addition, with regard to wiring, the width of the electrode part is now 6μ instead of the conventional 10μ due to the present invention.
This made it possible to increase the density of wiring.

なお、本発明による抵抗はコンタクト部の面積が従来例
より小さくなっているが、コンタクト窓4μ口でコンタ
クト抵抗は20Ω程度なので、それを考慮してあらかじ
め抵抗設計を行なえば良く、欠点とならない。
Although the area of the contact portion of the resistor according to the present invention is smaller than that of the conventional example, since the contact resistance is about 20Ω with a contact window of 4 μm, it is sufficient to take this into consideration when designing the resistor in advance, and this is not a drawback.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明によるシリコン被膜抵抗の平面図、第2
図は第1図の断面図、第3図は従来の被膜抵抗の平面図
、第4図は第3図の断面図である。 1・・・絶縁膜、   2・・・シリコン被膜。 3・・・絶縁膜、   4・・・電極。
FIG. 1 is a plan view of a silicon film resistor according to the present invention, and FIG.
The figures are a sectional view of FIG. 1, FIG. 3 is a plan view of a conventional film resistor, and FIG. 4 is a sectional view of FIG. 3. 1... Insulating film, 2... Silicon coating. 3... Insulating film, 4... Electrode.

Claims (1)

【特許請求の範囲】[Claims] 第1絶縁膜上に選択的に形成されたシリコン被膜を完全
に被うように付着された第2絶縁膜を具備し、前記シリ
コン被膜上においてシリコン被膜の周縁から所定の距離
をおいた少なくとも2つの開口部を有し、前記シリコン
被膜と前記第2絶縁膜上の電極とを接続してなる半導体
集積回路用抵抗。
A second insulating film is attached to completely cover a silicon film selectively formed on the first insulating film, and at least two insulating films are disposed on the silicon film at a predetermined distance from a periphery of the silicon film. A resistor for a semiconductor integrated circuit, which has two openings and connects the silicon film and an electrode on the second insulating film.
JP16303386A 1986-07-11 1986-07-11 Resistor for semiconductor integrated circuit Pending JPS6318656A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16303386A JPS6318656A (en) 1986-07-11 1986-07-11 Resistor for semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16303386A JPS6318656A (en) 1986-07-11 1986-07-11 Resistor for semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS6318656A true JPS6318656A (en) 1988-01-26

Family

ID=15765908

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16303386A Pending JPS6318656A (en) 1986-07-11 1986-07-11 Resistor for semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS6318656A (en)

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