JPS6165464A - Manufacture of film resistor in thick film multilayer substrate - Google Patents

Manufacture of film resistor in thick film multilayer substrate

Info

Publication number
JPS6165464A
JPS6165464A JP18756484A JP18756484A JPS6165464A JP S6165464 A JPS6165464 A JP S6165464A JP 18756484 A JP18756484 A JP 18756484A JP 18756484 A JP18756484 A JP 18756484A JP S6165464 A JPS6165464 A JP S6165464A
Authority
JP
Japan
Prior art keywords
resistor
layer
trimming
multilayer substrate
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18756484A
Other languages
Japanese (ja)
Inventor
Shiro Ezaki
江崎 史郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP18756484A priority Critical patent/JPS6165464A/en
Publication of JPS6165464A publication Critical patent/JPS6165464A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01CRESISTORS
    • H01C17/00Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/22Apparatus or processes specially adapted for manufacturing resistors adapted for trimming
    • H01C17/24Apparatus or processes specially adapted for manufacturing resistors adapted for trimming by removing or adding resistive material
    • H01C17/242Apparatus or processes specially adapted for manufacturing resistors adapted for trimming by removing or adding resistive material by laser
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistors, capacitors or inductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Plasma & Fusion (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To facilitate the trimming of the resistor of the lower circuit layer by a method wherein the interlayer insulation layer at the part opposed to the part of trimming of the lower circuit layer is formed thinly in manufacture of the titled substrate. CONSTITUTION:The lower layer wiring conductors 28 and 29 and the lower layer resistor 30 are formed on an insulation substrate 27 of alumina or the like. Next, interlayer insulation layers 32 and 33 are formed, and the upper wiring conductors 35, 36, and 37 and the upper layer resistor 38 are formed on the insulation layer 33. At this time, the part of the insulation layer 33 opposed to the part of trimming of the lower resistor 30 is provided with an aperture 34, and the insulation layer is thinned at this part. Then, the laser output does not have to be much increased in trimming 40 to the lower layer resistor 30, and trimming is facilitated; besides, its time is saved. Since the lower layer resistor 30 can be subjected to trimming after calcination of the upper layer circuits, the resistance value of the lower layer resistor 30 can be accurately set.

Description

【発明の詳細な説明】 [発明の技術分野] この発明は、厚膜多層基板における膜抵゛抗体の製造方
法に係り、特に下層側に形成された抵抗体のトリミング
を容易にし、該抵抗体の抵抗値を正確に設定し得るよう
にしたものに関する。
Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a method for manufacturing a film resistor on a thick film multilayer substrate, and in particular, it facilitates trimming of a resistor formed on the lower layer side. This invention relates to a device that allows the resistance value of the device to be set accurately.

C発明の技術的背景] 周知のように、近時では、電子機器等の小形軽量化を図
るために、混成集積回路が多く使用されるようになって
きている。この混成集積回路は、一般に、絶縁基板に導
体材料及び抵抗材料を印刷してなる回路層の形成された
厚膜基板に、リード線のないチップタイプの受動素子や
能動素1子を半田付けして構成されるものである。
C. Technical Background of the Invention] As is well known, in recent years, hybrid integrated circuits have come into widespread use in order to reduce the size and weight of electronic devices and the like. This hybrid integrated circuit generally consists of a thick film substrate on which a circuit layer is formed by printing a conductive material and a resistive material on an insulating substrate, and a single chip-type passive element or active element without lead wires is soldered to the thick film substrate. It is composed of

ところで、上記のような厚膜基板においては、回路の高
密度実装化を図るために、回路層を絶縁層を介して多層
に形成することが行なわれている。
By the way, in the thick film substrate as described above, in order to achieve high-density packaging of circuits, circuit layers are formed in multiple layers with insulating layers interposed therebetween.

第3図は、このような厚膜多層基板の従来の製造方法を
説明するためのものである。まず、例えばアルミナ等の
セラミック材料で形成された絶縁基板11上に、下層配
線導体12.13及び下層抵抗体14を形成し、第1の
回路層15を構成する。この下層配線導体12.13は
、例えば銀−パラジウム系ペーストをスクリーン印刷法
で印刷し800〜900℃の高温で酸化雰囲気中で焼成
することにより形成される。また、上記下層抵抗体14
は、例えば酸化ルテニウム系ペーストを上記と同様に印
刷・焼成することにより形成されるものである。そして
、上記下層抵抗体14に、例えばレーザトリミング法や
サンドブラスト法等によりトリミング(切り込み16)
を施して、その抵抗値を設定する。
FIG. 3 is for explaining a conventional manufacturing method of such a thick film multilayer substrate. First, lower layer wiring conductors 12 and 13 and lower layer resistor 14 are formed on insulating substrate 11 made of a ceramic material such as alumina to constitute first circuit layer 15. The lower wiring conductor 12.13 is formed, for example, by printing a silver-palladium paste using a screen printing method and firing it in an oxidizing atmosphere at a high temperature of 800 to 900°C. In addition, the lower layer resistor 14
is formed, for example, by printing and firing a ruthenium oxide paste in the same manner as above. Then, the lower resistor 14 is trimmed (notches 16) by, for example, a laser trimming method or a sandblasting method.
to set its resistance value.

その後、上記第1の回路層15上に、例えばガラス系ペ
ーストの印刷・焼成を2回繰り返して2層の絶縁層17
.48を形成し、図中上側の絶縁層18上に上記と同様
にして上層配線導体19〜21及び上層抵抗体22を形
成し第2の回路層23を構成する。そして、上記上層抵
抗体22にトリミング(切り込み24)を施してその抵
抗値を設定し、ここに厚膜多層基板が構成されるもので
ある。
Thereafter, printing and baking of, for example, a glass-based paste is repeated twice on the first circuit layer 15 to form a two-layer insulating layer 17.
.. 48, and the upper layer wiring conductors 19 to 21 and the upper layer resistor 22 are formed on the insulating layer 18 on the upper side in the figure in the same manner as described above to constitute the second circuit layer 23. Then, the upper layer resistor 22 is trimmed (cuts 24) to set its resistance value, thereby constructing a thick film multilayer substrate.

[背景技術の問題点] しかしながら、上記のような従来の厚膜多層基板の製造
方法では、下層抵抗体14のトリミング終了後、つまり
下層抵抗体14の抵抗値が設定された後に、絶縁層17
.18や上層配線導体19〜21及び上層抵抗体22等
を形成するために高温での焼成が繰り返されるので、下
層抵抗体14の抵抗値がトリミング時の設定値から大き
く変動してしまうという問題が生じる。そして、特にこ
の抵抗値の変動幅は、約10%にも及ぶ場合があるため
、下層抵抗体14としては、高精度の抵抗値が必要とさ
れる回路への適用ができないという不都合が生じるもの
である。また、下層抵抗体14のトリミング工程と、上
層抵抗体22のトリミング工程とを別個に行なっている
ため、製造工程が煩雑になるという問題も有している。
[Problems with Background Art] However, in the conventional thick film multilayer substrate manufacturing method as described above, after trimming of the lower resistor 14 is completed, that is, after the resistance value of the lower resistor 14 is set, the insulating layer 17 is
.. 18, upper layer wiring conductors 19 to 21, upper layer resistor 22, etc., firing at high temperatures is repeated, so there is a problem that the resistance value of lower layer resistor 14 varies greatly from the setting value at the time of trimming. arise. In particular, since the fluctuation range of this resistance value can reach as much as about 10%, the lower layer resistor 14 has the disadvantage that it cannot be applied to circuits that require a highly accurate resistance value. It is. Further, since the trimming process for the lower layer resistor 14 and the trimming process for the upper layer resistor 22 are performed separately, there is also a problem that the manufacturing process becomes complicated.

そこで、近時では、第4図に示すような手段(特開昭5
9−9997号公報参照)が考えられている。
Therefore, in recent years, the method shown in Fig. 4 (Japanese Patent Laid-Open No. 5
9-9997) is being considered.

すなわち、これは、下層抵抗体14の形成後トリミング
を行なわず、第1の回路層15.絶縁層17.18及び
第2の回路層23が全て形成された後、下層抵抗体14
に対して絶縁層18の上から例えばレーザ光を照射して
トリミング(切り込み25)を施すとともに、上層抵抗
体22にトリミング(切り込み26)を施すようにして
いるしのである。
That is, this means that the first circuit layer 15 . without trimming after forming the lower resistor 14 . After the insulating layers 17, 18 and the second circuit layer 23 are all formed, the lower resistor 14
For example, a laser beam is irradiated onto the insulating layer 18 to perform trimming (notches 25), and the upper layer resistor 22 is also trimmed (notches 26).

ところが、上記のような手段では、2層の絶縁層17.
18全体の膜厚は通常40〜50μmにもなるため、絶
縁層17.18を介して下層抵抗体14をトリミングす
ることが技術的に極めて困難になるという問題を有して
いる。例えばレーザトリミングを行なう場合には、レー
ザの出力を高めかつトリミングスピードを低くしなけれ
ばならないもので、非常に時間がかかるとともに、抵抗
値の精度も直接トリミングを施すものに比して劣化する
ものである。
However, with the above-mentioned means, the two-layer insulating layer 17.
Since the film thickness of the entire resistor 18 is usually 40 to 50 μm, there is a problem in that it is technically extremely difficult to trim the lower resistor 14 through the insulating layer 17, 18. For example, when performing laser trimming, the laser output must be increased and the trimming speed must be reduced, which is extremely time consuming and results in poor resistance accuracy compared to direct trimming. It is.

[発明の目的] この発明は上記事情を考慮しなされたもので、下層側に
形成された抵抗体の抵抗値を変動させることなく正確に
設定し財るとともに、製造工程も簡易化し得る観めで良
好な厚膜多層基板における膜抵抗体の製造方法を1足供
することを目的とする。
[Object of the Invention] The present invention has been made in consideration of the above circumstances, and has the aim of accurately setting the resistance value of the resistor formed on the lower layer side without changing it, and also simplifying the manufacturing process. The purpose of this invention is to provide a method for manufacturing a film resistor using a good thick film multilayer substrate.

[発明の概要] すなわち、この発明に係る厚膜多層基板における膜抵抗
体の製造方法は、絶縁基体上に抵抗体を含む第1の回路
層を形成する第1の工程と、この第1の工程の後前記第
1の回路層上に前記抵抗体のトリミング部分と対向する
部分の膜厚を薄くして絶縁層を形成する第2の工程と、
この第2の工程の後前記絶縁層上に第2の回路層を形成
する第3の工程と、この第3の工程の後前記絶縁層の膜
厚の薄い部分を介して前記抵抗体のトリミングを行なう
第4の工程とを具備することにより、下層側に形成され
た抵抗体の抵抗値を変動させることなく正確に設定し寿
るとともに、製造工程も簡易 ′化し得るようにしたも
のである。
[Summary of the Invention] That is, the method for manufacturing a film resistor in a thick film multilayer substrate according to the present invention includes a first step of forming a first circuit layer including a resistor on an insulating substrate; After the step, a second step of forming an insulating layer on the first circuit layer by reducing the film thickness of a portion facing the trimmed portion of the resistor;
After this second step, a third step of forming a second circuit layer on the insulating layer; and after this third step, trimming the resistor through a thin portion of the insulating layer. By providing a fourth step of performing the above, it is possible to accurately set the resistance value of the resistor formed on the lower layer side without changing it and to simplify the manufacturing process. .

[発明の実施例] 以下、この発明の一実施例について図面を参照して詳細
に説明する。第1図及び第2図において、まず、例えば
アルミナ等のセラミック材料で形成された絶縁基板21
上に、下層配線導体28.29及び下層抵抗体30を形
成し、第1の回路層31を構成する。この下層配線導体
28.29は、例えば銀−パラジウム系ペーストをスク
リーン印刷法で印刷し800〜900℃の^濡で酸化雰
囲気中で焼成することにより形成される。また、上記下
層抵抗体30は、例えば酸化ルテニウム系ペーストを上
記と同様に印刷・焼成することにより形成されるもので
ある。
[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. 1 and 2, first, an insulating substrate 21 made of a ceramic material such as alumina, etc.
Lower layer wiring conductors 28 and 29 and lower layer resistor 30 are formed on top to form a first circuit layer 31. The lower wiring conductors 28 and 29 are formed, for example, by printing a silver-palladium paste using a screen printing method and firing the paste at 800 to 900° C. in an oxidizing atmosphere. Further, the lower layer resistor 30 is formed, for example, by printing and baking a ruthenium oxide paste in the same manner as described above.

その後、上記下層抵抗体30にトリミングを施すことな
く、上記第1の回路層31上に、例えばガラス系ペース
トの印刷・焼成を2回繰り返して、2層の絶縁層32.
33を形成する。この場合、図中上側の絶縁層33は、
下層抵抗体30のトリミング部分に対応する位置に開口
部34を有するように形成され、結局絶縁層32.33
を合わせた膜厚が下層抵抗体30のトリミング部分に対
応する部分だけ薄くなるように形成されているものであ
る。
Thereafter, without trimming the lower resistor 30, printing and firing of, for example, a glass-based paste is repeated twice on the first circuit layer 31 to form a two-layer insulating layer 32.
form 33. In this case, the upper insulating layer 33 in the figure is
It is formed to have an opening 34 at a position corresponding to the trimmed portion of the lower resistor 30, and as a result, the insulating layer 32, 33
The combined thickness of the lower resistor 30 is made thinner in the portion corresponding to the trimmed portion of the lower resistor 30.

そして、上記絶縁層33上に、上記と同様にして上層配
線導体35〜37及び上層抵抗体38を形成し第2の回
路層39を構成する。その後、上記下層抵抗体30に上
記絶縁層33の開口部34を介してトリミング(切り込
み40)を施すとともに、同時に、上層抵抗体38にも
トリミング(切り込み41)を施し、ここに厚膜多層基
板が構成されるものである。
Then, upper layer wiring conductors 35 to 37 and upper layer resistor 38 are formed on the insulating layer 33 in the same manner as described above to constitute a second circuit layer 39. Thereafter, the lower layer resistor 30 is trimmed (cut 40) through the opening 34 of the insulating layer 33, and at the same time, the upper layer resistor 38 is also trimmed (cut 41), and the thick film multilayer substrate is composed of

したがって、上記実施例によれば、第1の回路層31.
第2の回路層39及び絶縁層32.33等が全て印刷・
焼成された後に下層抵抗体30のトリミングを行なうと
ともに、絶縁層32.33を合わせた膜厚が下層抵抗体
30のトリミング部分に対応する部分だけ薄くなってい
るので、トリミング作業が容易にでき下層抵抗体30の
抵抗値を正確に設定することができ、高精度の抵抗値が
必要とされる回路への通用を可能にすることができる。
Therefore, according to the above embodiment, the first circuit layer 31.
The second circuit layer 39, insulating layers 32, 33, etc. are all printed/printed.
After firing, the lower resistor 30 is trimmed, and since the combined thickness of the insulating layers 32 and 33 is thinner in the portion corresponding to the trimmed portion of the lower resistor 30, trimming can be done easily and the lower resistor 30 can be trimmed. The resistance value of the resistor 30 can be set accurately, and it can be used in circuits that require highly accurate resistance values.

また、下層抵抗体30と上層抵抗体39とを同時にトリ
ミングすることができるので、トリミング工程が1回で
すみ、製造が簡易化されるものである。
Further, since the lower layer resistor 30 and the upper layer resistor 39 can be trimmed at the same time, the trimming process is only performed once, and manufacturing is simplified.

ここで、上記実施例では、第1の回路層31及び第2の
回路1i139に共に抵抗体30.38を形成するよう
にしたが、これは第1の回路層31にのみ抵抗体30が
形成されるものや、低抗体が3層以上の多層構造になっ
ているもの等にも適用し得ることは言うまでもないこと
である。また、絶縁層33に形成された開口部34とし
ては、例えばL字状や円形状等適宜設定し得るとともに
、1つの下層抵抗体に対して複数形成するようにしても
よいものである。
Here, in the above embodiment, the resistor 30.38 is formed in both the first circuit layer 31 and the second circuit 1i139, but this means that the resistor 30 is formed only in the first circuit layer 31. Needless to say, the present invention can also be applied to those with a multilayer structure of three or more layers of low antibodies. Further, the openings 34 formed in the insulating layer 33 may be appropriately set, for example, in an L-shape or a circular shape, and a plurality of openings may be formed for one lower layer resistor.

ざらに、絶縁層33に開口部34を形成するのに限らず
、絶縁層32に開口部を形成して絶縁層32.33を合
わせた膜厚を薄くするようにしてもよいものである。ま
た、上記のような高温焼成型厚膜多層基板に限らず、樹
脂系の低温硬化型厚膜多層基板にも実施し得るものであ
る。
In other words, instead of forming the opening 34 in the insulating layer 33, an opening may be formed in the insulating layer 32 to reduce the combined thickness of the insulating layers 32 and 33. Furthermore, the present invention is not limited to the high-temperature firing type thick-film multilayer substrate as described above, but can also be applied to a resin-based low-temperature curing type thick-film multilayer substrate.

なお、この発明は上記実施例に限定されるものではなく
、この外その要旨を逸脱しない範囲で種々変形して実施
することができる。
It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the gist thereof.

E発明の効果] したがって、以上詳述したようにこの発明によれば、下
層側に形成された低抗体の抵抗値を変動させることなく
正確に設定し得るとともに、製造工程も簡易化し得る(
転めて良好な厚膜多層基板における膜抵抗体の製造方法
を提供することができる。
E Effects of the Invention] Therefore, as detailed above, according to the present invention, it is possible to accurately set the resistance value of the low antibody formed on the lower layer side without changing it, and the manufacturing process can also be simplified (
This makes it possible to provide a method for manufacturing a film resistor in a thick film multilayer substrate that is superior in quality.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図はそれぞれこの発明に係る厚膜多層基
板における膜抵抗体の製造方法の一実施例を示す側断面
図及び平面図、第3図及び第4図はそれぞれ従来の厚膜
多層基板における膜抵抗体の製造方法を示す側断面図で
ある。 11・・・絶縁基板、12.13・・・下層配線導体、
14・・・下層抵抗体、15・・・第1の回路層、16
・・・切り込み、11゜18・・・絶縁層、19〜21
・・・上層配線導体、22・・・上層抵抗体、23・・
・第2の回路層、24・・・切り込み、25.26・・
・切り込み、27・・・絶縁基板、28.29・・・下
層配線導体、30・・・下層抵抗体、31・・・第1の
回路層、32.33・・・絶縁層、34・・・開口部、
35〜37・・・上層配線導体、38・・・上層抵抗体
、39・・・第2の回路層、40.41・・・切り込み
1 and 2 are a side sectional view and a plan view, respectively, showing an embodiment of the method for manufacturing a film resistor in a thick film multilayer substrate according to the present invention, and FIGS. FIG. 2 is a side sectional view showing a method for manufacturing a film resistor in a multilayer substrate. 11... Insulating substrate, 12.13... Lower layer wiring conductor,
14... Lower layer resistor, 15... First circuit layer, 16
...Cut, 11°18...Insulating layer, 19-21
...Upper layer wiring conductor, 22...Upper layer resistor, 23...
・Second circuit layer, 24...notch, 25.26...
- Notch, 27... Insulating substrate, 28. 29... Lower layer wiring conductor, 30... Lower layer resistor, 31... First circuit layer, 32. 33... Insulating layer, 34... ·Aperture,
35-37... Upper layer wiring conductor, 38... Upper layer resistor, 39... Second circuit layer, 40.41... Notch.

Claims (2)

【特許請求の範囲】[Claims] (1)絶縁基体上に抵抗体を含む第1の回路層を形成す
る第1の工程と、この第1の工程の後前記第1の回路層
上に前記抵抗体のトリミング部分と対向する部分の膜厚
を薄くして絶縁層を形成する第2の工程と、この第2の
工程の後前記絶縁層上に第2の回路層を形成する第3の
工程と、この第3の工程の後前記絶縁層の膜厚の薄い部
分を介して前記抵抗体のトリミングを行なう第4の工程
とを具備してなることを特徴とする厚膜多層基板におけ
る膜抵抗体の製造方法。
(1) A first step of forming a first circuit layer including a resistor on an insulating substrate, and a portion facing the trimmed portion of the resistor on the first circuit layer after this first step. a second step of forming an insulating layer by thinning the film thickness; a third step of forming a second circuit layer on the insulating layer after this second step; A method for manufacturing a film resistor in a thick film multilayer substrate, comprising: a fourth step of trimming the resistor through a thin portion of the insulating layer.
(2)上記第2の工程は、複数の絶縁層を多層に形成し
、所定の絶縁層の上記抵抗体のトリミング部分と対向す
る部分に開口部を形成することにより、絶縁層全体の膜
厚を薄くするようにしてなることを特徴とする特許請求
の範囲第1項記載の厚膜多層基板における膜抵抗体の製
造方法。
(2) In the second step, a plurality of insulating layers are formed in multiple layers, and an opening is formed in a portion of a predetermined insulating layer that faces the trimmed portion of the resistor, thereby increasing the thickness of the entire insulating layer. 2. A method of manufacturing a film resistor in a thick film multilayer substrate according to claim 1, wherein the film resistor is made thinner.
JP18756484A 1984-09-07 1984-09-07 Manufacture of film resistor in thick film multilayer substrate Pending JPS6165464A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18756484A JPS6165464A (en) 1984-09-07 1984-09-07 Manufacture of film resistor in thick film multilayer substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18756484A JPS6165464A (en) 1984-09-07 1984-09-07 Manufacture of film resistor in thick film multilayer substrate

Publications (1)

Publication Number Publication Date
JPS6165464A true JPS6165464A (en) 1986-04-04

Family

ID=16208289

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18756484A Pending JPS6165464A (en) 1984-09-07 1984-09-07 Manufacture of film resistor in thick film multilayer substrate

Country Status (1)

Country Link
JP (1) JPS6165464A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6471147A (en) * 1987-08-12 1989-03-16 American Telephone & Telegraph Solid state circuit with laser-fusible link
US5439732A (en) * 1993-01-22 1995-08-08 Nippondenso Co., Ltd. Ceramic multi-layer wiring board
US5593722A (en) * 1992-12-22 1997-01-14 Nippondenso Co., Ltd. Method of producing thick multi-layer substrates
US7105911B2 (en) 2002-10-16 2006-09-12 Hitachi, Ltd. Multilayer electronic substrate, and the method of manufacturing multilayer electronic substrate
JP5397539B2 (en) * 2010-03-31 2014-01-22 株式会社村田製作所 Multilayer ceramic substrate and manufacturing method thereof

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6471147A (en) * 1987-08-12 1989-03-16 American Telephone & Telegraph Solid state circuit with laser-fusible link
US5593722A (en) * 1992-12-22 1997-01-14 Nippondenso Co., Ltd. Method of producing thick multi-layer substrates
DE4343934B4 (en) * 1992-12-22 2005-08-25 Denso Corp., Kariya Method for producing multiple thick-film substrates
US5439732A (en) * 1993-01-22 1995-08-08 Nippondenso Co., Ltd. Ceramic multi-layer wiring board
US5562973A (en) * 1993-01-22 1996-10-08 Nippondenso Co. Ltd. Ceramic multi-layer wiring board
US7105911B2 (en) 2002-10-16 2006-09-12 Hitachi, Ltd. Multilayer electronic substrate, and the method of manufacturing multilayer electronic substrate
JP5397539B2 (en) * 2010-03-31 2014-01-22 株式会社村田製作所 Multilayer ceramic substrate and manufacturing method thereof
US8754742B2 (en) 2010-03-31 2014-06-17 Murata Manufacturing Co., Ltd. Multilayer ceramic substrate and method for producing the same

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