JPS63201347U - - Google Patents

Info

Publication number
JPS63201347U
JPS63201347U JP1987092071U JP9207187U JPS63201347U JP S63201347 U JPS63201347 U JP S63201347U JP 1987092071 U JP1987092071 U JP 1987092071U JP 9207187 U JP9207187 U JP 9207187U JP S63201347 U JPS63201347 U JP S63201347U
Authority
JP
Japan
Prior art keywords
lead frame
fet
tip
arrangement
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987092071U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987092071U priority Critical patent/JPS63201347U/ja
Publication of JPS63201347U publication Critical patent/JPS63201347U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図〜第３図は本考案の実施例を示し、第１
図は打抜き加工時における各リードフレームの配
列を示す平面図、第２図はＦＥＴコネクタの製造
過程説明図、第３図は第二実施例における各リー
ドフレームの配列を示す平面図、第４図は従来例
におけるリードフレームの配列を示す平面図であ
る。 １……帯状材、２……連鎖帯、６……半導体部
、７……ワイヤ、８……送り孔、９，１０，１１
……リードフレーム、１２……連結部、１３……
樹脂パツケイジ、１４…ホルダー、１５…ハウジ
ング、１６……放熱性樹脂。

Claims (1)

    【実用新案登録請求の範囲】
  1. 帯状材より打抜き加工成形されるＦＥＴのリー
    ドフレームの先端をタブ端子化したＦＥＴコネク
    タにおいて、上記の打抜き加工される３つのリー
    ドフレームの配列を少くとも１本のリードフレー
    ムを別方向に向けた形状に配列することを特徴と
    するリードフレーム。
JP1987092071U 1987-06-17 1987-06-17 Pending JPS63201347U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987092071U JPS63201347U (ja) 1987-06-17 1987-06-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987092071U JPS63201347U (ja) 1987-06-17 1987-06-17

Publications (1)

Publication Number Publication Date
JPS63201347U true JPS63201347U (ja) 1988-12-26

Family

ID=30953437

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987092071U Pending JPS63201347U (ja) 1987-06-17 1987-06-17

Country Status (1)

Country Link
JP (1) JPS63201347U (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57177548A (en) * 1981-04-06 1982-11-01 Int Rectifier Corp Module for semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57177548A (en) * 1981-04-06 1982-11-01 Int Rectifier Corp Module for semiconductor device

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