JPH0446543U - - Google Patents

Info

Publication number
JPH0446543U
JPH0446543U JP1990089048U JP8904890U JPH0446543U JP H0446543 U JPH0446543 U JP H0446543U JP 1990089048 U JP1990089048 U JP 1990089048U JP 8904890 U JP8904890 U JP 8904890U JP H0446543 U JPH0446543 U JP H0446543U
Authority
JP
Japan
Prior art keywords
substrate
metal wire
thin metal
lead base
semiconductor pellet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990089048U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990089048U priority Critical patent/JPH0446543U/ja
Publication of JPH0446543U publication Critical patent/JPH0446543U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07141—Means for applying energy, e.g. ovens or lasers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図は本考案に係る半導体装置の斜視断面図
、第２図ａ，ｂ，ｃ，ｄはリードとワイヤをカシ
メ固定する際の工程説明図、第３図ａ，ｂ、第４
図ａ，ｂ、第５図ａ，ｂの他の実施例を示すもの
であつて夫々ａはカシメ固定する前のリードの斜
視図、ｂはカシメ固定した後のリード長手方向で
の断面図、第６図ａ，ｂは従来のワイヤボンデイ
ング工程を示すもので、ａはフアーストボンデイ
ング、ｂはセカンドボンデイングを示す工程説明
図、第７図は従来の半導体装置の斜視断面図を示
す。 １……半導体装置、２……基板、３……半導体
ペレツト、５……金属細線、６……リード基部。

Claims (1)

  1. 【実用新案登録請求の範囲】 基板上にマウントされた半導体ペレツトと基板
    周辺に配置されたリード基部とを金属細線で電気
    的に接続した半導体装置において、 上記半導体ペレツトから伸びる上記金属細線の
    端部を上記リード基部にカシメ固定したことを特
    徴とする半導体装置。
JP1990089048U 1990-08-24 1990-08-24 Pending JPH0446543U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990089048U JPH0446543U (ja) 1990-08-24 1990-08-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990089048U JPH0446543U (ja) 1990-08-24 1990-08-24

Publications (1)

Publication Number Publication Date
JPH0446543U true JPH0446543U (ja) 1992-04-21

Family

ID=31822753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990089048U Pending JPH0446543U (ja) 1990-08-24 1990-08-24

Country Status (1)

Country Link
JP (1) JPH0446543U (ja)

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