JPS6320908A - Adaptive digital filter - Google Patents

Abstract

PURPOSE:To speed up the converging speed of a variable coefficient of each variable coefficient multiplier by making inputs to the variable coefficient multipliers of the titled adaptive digital filters (ADFs) orthogonalized between the ADFs and in the ADFs themselves and making the square mean value to each input equal to each other. CONSTITUTION:An input um(k-1) to a unit delay element 19m-2 at a time (k) and a signal Rmum(k) being a multiple of Rm to an input um(k) to a unit delay element 19m-1 by a multiplier 22-m are added by a 1st adder 23-m, the result is multiplied with a variable coefficient Tm by a 1st variable coefficient multiplier 28-m to obtain a signal gm(k). Further, the signal um(k) is multiplied with a variable coefficient Sm by a 3rd variable coefficient multilier 24-m to obtain a signal fm(k). A signal being the result of multiplication of a variable coefficient cm(k) with the signal fm(k) by a 4th variable coefficient multiplier 25-m and a signal being the result of multiplication of a variable coefficient dm(k) by a 2nd variable coefficient multiplier 26-m are added by a 2nd adder 27-m to obtain an output ym(k) of an ADF-m at the same time (k), which is sent to an output terminal 11-m.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to an adaptive digital filter that can generate any transfer function, and in particular, an adaptive digital filter that has a high speed and is suitable for application to, for example, an echo canceller. It is related to.

(Prior Art) Recently, with the rapid progress of digital signal processing technology, adaptive digital filters have been developed.
1 Filter (hereinafter referred to as ADF) is attracting attention because of its wide range of application. A typical application example of ADF is its application to system identification. System identification means estimating the characteristics of an unknown system based on input/output data of the system whose characteristics are unknown.

FIG. 2 is a schematic diagram illustrating identification of an unknown system using ADF. In the figure, 41 is a signal input terminal, 42 is an estimation error output terminal, 43 is an unknown system, and 44 is an ADF.
, 45 is an adder. Also, x (k) is the input to the unknown system 43 and ADF 44 at time k, and y (k)
is the output of the unknown system 43 at time k, y (g) is the output of the ADF 44 at time k, e (k) is the time k
Estimation error in H = O, the characteristic of unknown system 43 'tADF
44 is assumed to be correctly estimated.

An echo canceller is a specific example of the use of ADFe as described above. This echo canceller.

For example, in recent years it has been applied to remote conference systems that meet high demand. FIG. 3 is a diagram schematically showing a configuration when an echo canceller is applied to a remote conference system. In the figure, 51-1. .

51-2 is a microphone, 52-1 and 52-2 are speakers, 53-1 and 53-2 are echo cancellers, and 54
-1゜54-2 is a transmission line, -1 and 55-2 are ADF,
56-1 and 56-2 are acoustic coupling paths. Generally, remote conference systems use audio terminals with integrated speakers and microphones, as shown in Figure 3. Therefore, acoustic coupling occurs between the speakers and microphones.
As a result, the signal output from the loudspeaker goes around to the microphone, significantly degrading the quality of the call. In the example of FIG. 3, acoustic coupling paths 56-1 and 56-2 are formed between the speaker 52-1 and the microphone 51-1 and between the speaker 52-2 and the microphone 51-2, respectively. However, echo cancellers 53-1, 53-
2', loop signals from the speaker to the microphone can be removed.

Echo canceller ADF like the one above! : Then,
Conventionally, an ADF as shown in Figure 4 has been used (for example, ``1985 National Conference of the Information and Systems Division of the Institute of Electronics and Communication Engineers J, 366, p2-107).In Figure 4, this ADF is (an integer greater than or equal to MFit) basic sections.One basic section consists of a second-order cyclic digital filter Fl, excluding the M-th basic section.
(having one unit time delay elements 62-1 and 63-1'i), a second-order acyclic digital filter F2, and a first-order acyclic digital filter F3t. The second-order acyclic digital filter F2 has a zero point at a position that is a mirror image of the unit circle of the second-order cyclic digital filter. The M-th basic section includes a second-order cyclic digital filter and a first-order acyclic digital filter.

The first output 0UTI of each of the M basic intervals is connected to the input of the adder 64, and the output of the adder 64 becomes the output of the ADF. The second of each basic interval from the 1st to the (M-1)th
The output 0UT2 of is connected to the input of the next stage. Also,
The input of the first basic section becomes the input of the ADF.

In the ADF configured in this way, each variable coefficient is pt l qt l pt l qt m ”'+
Variable coefficient multipliers 60-1, 61- which are pM+qM
1, 60-2, 61-2. ..., 60-M,
Each input signal φ, (k.

φ+0c-t), φ1(k), φt(k-t),...
,φu(kl.

The following relationship holds true between φM(k-1).

However, 1 zl + 2 +..., M; J = 1, 2
．． ....

M; i←l, where indicates the averaging operation for time k. That is, the inputs to the variable coefficient multipliers between ADF-i and ADF-/ are orthogonal to each other.

(Problems to be solved by the invention) However, in the conventional ADF as shown in FIG.
As shown in the following formula, φt(Wφ1(k-t) God O...
12+ (However, 1 ” le 2 +..., M)
The input signal φi(W) of the variable coefficient multiplier 60-1 and the input signal φ1(k
−t) is not O, and the input signal φ
, (silk, φ*(k), ..., φu(k)).

φ1(k)←φei) (However, i←E)・・・・・・
...(3), variable coefficient P+, (11, P2.
(12,...

The problem that the convergence speed of pM l qM is slow is often encountered.

The present invention solves the problems of the conventional ADFO described above,
ADFt' with fast convergence speed of variable coefficients of variable coefficient multiplier
The purpose is to provide.

(Means for solving the problem) The present invention connects M basic sections (M is the number of lines of 1 or more) in cascade.

Each of the (M-1)th basic sections connected in cascade in order has an input terminal, a first output terminal, and a second output terminal,
On the other hand, the M-th basic section has an input terminal and a first output terminal, the input terminal of the first basic section constitutes the signal input terminal of the adaptive digital filter, and each basic section from the second to the M-th An adaptive digital filter in which the input terminal of a section is connected to the second output terminal of the basic section immediately before it, and the sum of the signals obtained at the first output terminal of each basic section is the output of the adaptive digital filter. Target filter.

The present invention provides a first adaptive digital filter.
Then, a path from the input terminal of each of the M basic sections to the first output terminal is connected to a second-order cyclic digital filter and a circuit whose input is connected to the zero-order acyclic circuit of the second-order cyclic digital filter. It is constructed by cascading a second acyclic digital filter.

Second, the path from the input terminal to the second output terminal of each basic section from the first to the (M-1)th period is created by connecting the second-order cyclic digital filter and the second-order acyclic digital filter. Configure by connection.

Third, the first-order acyclic digital filter in each of the 1m-th (l≦m≦M) basic sections is divided into a signal obtained by multiplying the input signal um(k) by a coefficient Rm in a multiplier, and a time signal. A first adder adds the signal um(k-1) input to the first-order acyclic digital filter at -1, and a first variable coefficient multiplier adds a variable coefficient m to the output. -multiply,
Furthermore, the signal dm(k)・g m(
k), the signal u m[k) is multiplied by a variable coefficient Sm by a third variable coefficient multiplier, and the output m(k) is multiplied by a variable coefficient cm(k)yk by a fourth variable coefficient multiplier. The multiplied signal cm(k) 1 m(k) is added by a second adder.

Fourth, the coefficient Rmt - the signal m(k) and gm(
kl are orthogonal to each other, and the variable coefficient cm(k
).

dm(k) (m = 1, 2, , , , M) is calculated sequentially at each time using a known adaptive control method (learning identification method, etc.) t
-Use and correct.

Fifth, the variable coefficients m and m are set to the second variable coefficients m and m.
and the fourth variable coefficient multiplier so that the root mean square values of the input signals to the fourth variable coefficient multiplier are equal.
When modifying m and ■m, the Sm-cm (ri and T'
S ・am (k) and Tm-d after m'am cry is corrected
Apart from the above-mentioned sequential correction, cmQc) and dm(k)' are corrected at certain fixed time intervals so that they are each equal to m(k).

Further, the present invention can be obtained by configuring the first-order acyclic digital filter as follows instead of the above configuration.

That is, a first-order acyclic digital filter is applied to a signal obtained by multiplying the signal um(k 1) one time before the signal um(k) inputted at time by a coefficient Rm'Th in a multiplier, and the un (k) in a first adder, its output is multiplied by a variable coefficient Sm in a first variable coefficient multiplier, and the output ■moc) is multiplied by a variable coefficient c m in a second variable coefficient multiplier. The signal e m(k) ・′■m(
k), the signal um(k-1) is multiplied by a variable coefficient m by a third variable coefficient multiplier, and the output gmfkl is
4th place.

Then, the coefficient Rmt−the signal f m (kl and g
rn) are orthogonal to each other, and the variable coefficient cm
[k) + dmQc) (m=t, 2,−,M)
is sequentially corrected at each time using a known adaptive control method (learning identification method, etc.).

The variable coefficients m and m are corrected at regular intervals so that the root mean square values of the input signals to the second and fourth variable coefficient multipliers are equal, and The above-mentioned sequential modification is such that when modifying, Sm-Cm(k) and Tm-dm(k) before modification are equal to Sm-Cm(k) and T'm'cm(k) after modification, respectively. separately cm
(kl and dm(k[-corrected at each certain period of time.

(Function) Input signal PI supplied to the input terminal of the first basic section
(k) is output to the second output terminal through the first multiplier, the second-order cyclic digital filter, and the second-order acyclic digital filter. The signal p t (kl) output from this second output terminal is supplied to the input terminal of the second basic section and output to the output terminal in the same manner as the first basic section. The signal P M (kl) is output from the second output terminal of the (M-1)th basic section and input to the Mth basic section.

On the other hand, the input signal pt(k) supplied to the input terminal of the first basic section passes through the first multiplier, the second-order cyclic digital filter, and the first-order acyclic digital filter, and is then sent to the first output terminal. A signal yt(k) is output. Similarly, P2(k
) is output as a signal yt(kJ) to the first output terminal.Similarly, ya(k),...1yM(k) are obtained from the first output terminal of the basic intervals up to the Mth. .These signals ys(k), ytQc),...

yM(k) is added and becomes the output of the digital filter.

The above action is common to the above two inventions.

Here, in the former invention, the first-order acyclic digital filter 7' is constructed as described above, and the coefficients Rm, , variable coefficients S m , Tm , cm(k), dm (k
) are set as described above, the input signals to the second and fourth variable coefficient multipliers are mutually orthogonalized in each basic interval, and the root mean square values of the input signals are equal to each other. Of course, the input signals to the second and fourth variable coefficient multipliers in the basic sections are also orthogonalized to each other.

Similarly, in the latter invention, the first-order acyclic digital filter is configured as described above, and the coefficient Rm and the variable coefficient S m+ T m+ c mQcl * d m(k
) 'eSince the settings are as above, the same effects can be obtained.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

1(a) to (C) are diagrams showing the configuration of an embodiment of the present invention, and FIG. 1(a) is a block diagram showing the basic configuration of the present embodiment.
Figure 7 (b) shows the ADF-m (mJ) in figure (a).
The circuit diagram showing the configuration of yM) and the circuit diagram [0] in the same figure (a
FIG. 1 is a circuit diagram showing the configuration of an ADF-M in a computer.

First, Figure 1 (a)? The basic configuration of this embodiment 0 will be explained with reference to FIG. The ADF according to this embodiment has the reference number 9.
It is indicated by a block indicated by a broken line. A.D.
As shown in the figure, F9 is ADF-1°ADF-2,
..., ADF-(M-1), and ADF-M are connected in cascade. In ADF-1, this input terminal 10
−1 at time, the signal Pt(kl(=x(k):
(k) is A according to this embodiment supplied from input terminal l.
) is input to DF9, and at the same time AD
At the same time, the signal P2(k) is sent to the input terminal 1O-2 of F-2 (this is an output terminal below Ruru 2 when viewed from the ADF-1, and this output terminal is referred to as the second output terminal). The signal yt(k)t- is outputted to the output terminal 11-1 of.

In the ADF-2, the signal P2 (k) is input from the input terminal 10-2 at a time, and at the same time, the signal P, (k)t- is sent to the input terminal 10-3 of the ADF-3. A signal yt (kl) is output to the first output terminal 11-2. Hereinafter, ADF-3, . . .

Similar processing is performed sequentially up to ADF-M.

In the final stage ADF-M, at the time from the input terminal 10-M, the second output terminal (10-M) of the ADF-(M-1) is connected.
The signal PM(k) sent from the terminal is input, and at the same time, the signal yM[k) is fully output to the first output terminal 11-M.

ADF-M does not have a second output terminal.

ADF-1, ADF-2, ..., ADF-(M-t)
.

Each first output terminal 11-1.11-2 of ADF-M
, ..., 11-(M-1), output y at 11-M
l(k), y2(k),...+'/M-1
(k) + VM(k) is added by the adder 8, and the result becomes the output y(kJ) of the ADF 9 at the time.

The output y (k) of the ADF 9 thus formed is subtracted from the output y [kl of the unknown system 3 by the adder 7, and a signal e (k) is output to the output terminal 2.

Next, the configuration of the ADF-m (m4M) will be explained with reference to FIG. 1(b). ADF-m (m to M) is fully equipped with a second-order recursive digital filter, a second-order non-recursive digital filter having a zero point at a mirror image position with respect to the unit circle of this filter, and a first-order non-recursive digital filter. It is composed of The second-order cyclic digital filter includes adders 13-m and 14-m, multipliers 15-m and 16-m,
Also, unit delay elements 19m-1 and 19m-2f are provided. The second-order acyclic digital filter has a unit delay element 1
9m-1 and 19m-21 multipliers 17-m and 18-
m% and adders 2O-rn and 21-mt-. The first-order acyclic digital filter has a unit delay element 19
m-1, first adder Z3- m, second adder 27-
m, multiplier 22-m, first variable coefficient multiplier 28-
m, a second variable coefficient multiplier 26-m, a third variable coefficient multiplier 26-m, and a fourth variable coefficient multiplier 25-m.
'f1-equipped.

As shown in the figure, the input of the first-order acyclic digital filter is connected to the zero-order acyclic circuit of the second-order acyclic digital filter.

Such components are υ-coupled with: First, the path from the input terminal 10-m to the first output terminal 11-m is constituted by a cascade connection of a second-order cyclic digital filter and a first-order acyclic digital filter, as shown in the figure. On the other hand, from the input terminal 10-m to the second
As shown in the figure, the path leading to the output terminal 10-(m+1) is composed of a cascade connection of a second-order cyclic digital filter and a second-order acyclic digital filter.

Next, the configuration of the ADF-M will be explained with reference to FIG. 1(C). The ADF-M includes a second-order recursive digital filter and a first-order acyclic digital filter. The second-order cyclic digital filter is an adder 13
-M and 14-M, multipliers 15-M and 16-M, and unit delay elements 19M-1 and 19M-2.

The first-order acyclic digital filter has a unit delay element of 19M.
-1, first adder -M, second adder 27-M, multiplier η-M, first variable coefficient multiplier 28-M, second variable coefficient multiplier 26-M, 3 variable coefficient multiplier 24-M
and a fourth variable coefficient multiplier 25-M'i. As shown in the figure, the input of the first-order acyclic digital filter is connected to the zero-order acyclic circuit of the second-order acyclic digital filter. As shown in the figure, the path from the input terminal 10-M of the ADF-M to the first output terminal 11-M is composed of a cascade connection of a second-order cyclic digital filter and a first-order acyclic digital filter. There is.

Next, the operation of this embodiment will be explained.

First, we will describe the operation of ADF-m (mJyM) shown in FIG. However, in the ADF-1, the signal X (-, that is, p+(k) input from the input terminal 1
input). At the same time k, multiplier 15-
Signal um(k-1) 'k am times signal am-
signal um(k-2)' with um(kl) and multiplier 16-m
(i'bm times the signal bm*um(k-L)t'' and the phase-inverted signal -bm'um(k-1) are sent to the adder 14-m
and the signal vm (kl 'f: obtained. The signal V
m (kl) and the signals P and m(k) are added at the same time to form a signal um(k). This signal um(kl is input to the unit delay element 19m-1 and has a unit delay of The signal um(k) input to the element 19m-1 is sequentially shifted through the unit delay elements 19m-1 and 19m-2i as time passes.

Furthermore, the input um(k-1) to the unit delay element 19m-2 at the same time k and the input um(k)t"am to the unit delay element 19m-1 at the multiplier 22-m are multiplied by the signal R.
m um(k) in the first adder Z3-m, and then multiplied by the variable coefficient Trnt in the first variable coefficient multiplier 28-m,
Signal ■m(k)'j: Obtain. Moreover, the signal um(k)
is converted into a variable coefficient Smt- by the third variable coefficient multiplier 24-m.
The signal fm(klf) is obtained by multiplying the signal fm(k) by the fourth variable coefficient multiplier 25-m.
A second adder 27-m adds the signal multiplied by 't- and the signal obtained by multiplying the signal g m (k) by a variable coefficient dm(k) in a second variable coefficient multiplier 26-m. , the output Vm(k) t- of the ADF-m at the same time k is obtained and sent to the output terminal 11-m. Also, at the same time k, the signal um(k-1) is multiplied by am in a multiplier 18-m, and the output am-un(k) is combined with the phase-inverted signal -am-um(k) and the signal um(k-2) by an adder 21-m.

The output and the signal um (bm in the ldt multiplier 17-m)
The multiplied signal is added by an adder 20-m, and the output Pm
+1 (1C) is the input terminal 10 of A DF - (m+1)
−(m+1).

Next, the operation of the ADF-M shown in FIG. 1(c) will be explained. At time k, signal PM(k) sent from ADF-(M-1) is input from input terminal 10-M. At the same time k, the signal uM(k-1) is generated by the 1 multiplier 15-M.
The signal am-ug (k-1) multiplied by eau and the multiplier 16-
The signal bM−uM(
k 1) t-phase inverted signal-bM-uM(k-1
) are added by an adder 14-M to obtain a signal vM(k). The signal VM(k) and the signal PM(kl) are added at the same time to become a signal uu(k).This signal uM(k)
becomes an input to the unit delay element 19M-1. The signal u M(k) inputted to the unit delay element 19M-1 at time is inputted to the unit delay element 19M-1, 19M-2 as time passes.
are sequentially shifted through . Further, the input u4(k-1) to the unit delay element 19M-2 at the same time k and the input uM(k) to the unit delay element 19M-1 at the multiplier 22-M are multiplied by tRM, RM-ug(k ) are added in an adder 23-M, and then multiplied by a variable coefficient TMe in a first variable coefficient multiplier path-M to obtain a signal gM(k)e. Further, the signal uM(k)t is multiplied by a variable coefficient SMt by a third variable coefficient multiplier 24-M to obtain a signal fM(kl'). 25-
The signal multiplied by the variable coefficient cM(kle) and the signal gM
(k) with a variable coefficient dM using a second variable coefficient multiplier 26-M.
The adder 27-M adds the signals multiplied by (k)e and the output yM(k)e of the ADF-M at the same time k, which is sent to the output terminal 11-M.

In the implementation Pi described above, ADF-m (m=t.

2,...,M) second and fourth variable coefficient multipliers 26
By orthogonalizing the input signals to -m and 25-m and making the root mean square values of these input signals equal to each other, the convergence speed of the variable coefficients cm(k) and dm(k) is increased. . This point will be explained in detail below.

As mentioned above, in conventional ADFs, ADF-i and ADF
-1 (where i←l), the inputs to the variable coefficient multiplier are orthogonal to each other as shown in equation (1) above, but ADF-i (i=1.2, ....

The inputs to the variable coefficient multiplier in M) are not orthogonal, as shown in equation (2) above. Moreover, each ADF-1 (t=
The root mean square values of the signals φ1 (kl) of t+2+..., M) are not equal, as shown in equation (3) above.

On the other hand, in this embodiment, in order to increase the convergence speed of the variable coefficients cm(kl, dm(k)) as described above, the variable coefficients are controlled as follows.

First, the second
In order to mutually orthogonalize the input signals to the and fourth variable coefficient multipliers 26-m and 25-m, the coefficient Rm is determined as follows.

■m(k) gm(kl = S m-um(k) ・T
From m(um(k-1)+Rm-um(kl) = 0, Rm can be found as Rm(m=t
+2,...,M) If t- is set, %ADF-1, AD
F-2, ..., variable coefficient multiplier 25-1 of ADF-M
．． 26-1.25-2.26-2,..., 25-M
, 26-M input signal fs(k)9g+(kl,fz
(k)1g2(k),...+fa (boundary.

gu(k) are mutually orthogonal.

Next, the signal f+ (k) 1g+ (k), f2
(k), gz(kl,...

In order to make all the root mean square values of fy(kl, gx(k) equal, the variable coefficients S+, Ts, S2,
Tx,..., SM.

Control is performed as follows. At certain intervals, the average value of the sum of the squares of the signal fm(k) 1 m(k) during that period is determined, and Sm and Tm are respectively the reciprocals of Fm and Gm, that is, Sm=1/Fm ( 6a) Tm=l/G
m (6b). At this time, at the same time, the values of Cm(k) and dm(k) are expressed as em[k) −8m cm(kl /Sm
(7a) d, dk) = Tm dm /Tm (7b
). Here, (OLD) is (5a) , (5b) , (6a) , (6b) every L time
, (7a) and (7b), the variable coefficient S m+Tm is changed according to each equation.

The values before change of c m (k) and dm (k), (NEW
) is the changed value. If you do this, (5a)
, (5b).

By changing Sm and ■m according to the formulas (6a) and (6b), the root mean square values of the signals fm(kl, ■m(k)) can be made equal, and each of (9a) and (9b) can be made equal. cm(k) according to the formula.

By changing d m (k), it is possible to suppress instantaneous level fluctuations in the output signals of the variable coefficient multipliers 26-m and 25-m caused by changes in Sm and ■m.

In the above manner, the variable coefficient multiplier 25-
The input to m and 26-m is ADF-n (however, m←n
) are mutually orthogonalized with the inputs to the variable coefficient multipliers of A
Two variable coefficient multipliers 25-m and 26- in DF-m
Each input to 6 is also orthogonal to each other, and all variable coefficient multipliers 25-1, 26-1. ....

The root mean square values of the inputs to 25-M and 26-M are equal. In this way, the variable coefficient multiplier 25-1 of the ADF9
．． 26-1. ..., 25-M, and 26-M is diagonalized and the diagonal elements are equal, so there is no variation in the inherent directivity of this matrix.

Therefore, the variable coefficient c+(kl, at(k), ”
・l CM(M+, dy(M+ adaptive control method known as easy-to-implement slope method (steepest descent method, learning identification method, etc.)
Even when using , the convergence speed is fast.

Next, another embodiment of the present invention will be described with reference to FIG. The basic configuration of this embodiment is as shown in FIG. 1(a),
Among these, ADF-m (m←M) is configured as shown in FIG. 5(a), and ADF-M is configured as shown in FIG. 5(b). This embodiment provides exactly the same effect as the previous embodiment shown in FIG. 1 described above. Hereinafter, only the parts different from the previous embodiment will be explained.

A D F −m (m
=1 + 2 +..., M), 29-m is a multiplier, 30-m is a first adder, 35-m is a second adder, and 31-m is a first variable coefficient multiplier. vessel, 32-m is the third
33-m is a second variable coefficient multiplier, and 34-m is a fourth variable coefficient multiplier. Such ADFm (m = 1 r 2 + ”' + M)
, the signal Pm(k) sent out from the ADF-(m-1) at time k is input from the input terminal 10-m, and the processing to obtain the signal um(k) and the signal um(kl +
u'm(k-1), u m(k-2) and signal P
The process of obtaining m+1(k)t- is the same as in the previous example (
However, in the ADF-M, as in the previous embodiment, the signal u
There is no process to obtain the signal P M+ t (k) than M(k) * uM(k-1) + uu(k-2).

).

The difference is that the second and fourth variable coefficient multipliers 33-m, 34-
This is the process of obtaining the input signals m(k) and m(k)e to m. At the same time k, unit delay element 19m-
input um(k) to unit 1 and human power um(k l)Fkcm to unit delay element 19m-2 in multiplier 29-m
@ did (Fji ”5 K m' um(k -1
) are added in an adder 30-m, and then multiplied by a variable coefficient 9m in a first variable coefficient multiplier 31-m to obtain a signal signal (chip).

Also, 'j, m (kl is the signal uH1(k-1
) is obtained by multiplying by the variable coefficient Tm by the k-th variable coefficient multiplier 32-m. The multiplication coefficient RmO value of the multiplier 29-m is the same as the multiplication coefficient RmO value of the multiplier 22-m in the previous embodiment, and the variable coefficient multiplier 31-m.

Variable coefficients Sm, T of 32-m, 33-m, 34-m
m.

cmQc) and dm(k) may be controlled using the same method as in the previous embodiment. If you do this, the ADF
-m second and fourth variable coefficient multipliers 33-m,
The inputs to 34-m are mutually orthogonal to the inputs to the corresponding variable coefficient multipliers of ADF-n (where m"rn), and the two variable coefficient multipliers 33-m within ADF-m.

Each input to 34-m is also orthogonal to each other, and all variable coefficient multipliers 33-1, 34-1, . . . , 33-M, 3
Since the root mean square values of the inputs to 4-M are equal, the convergence speed is fast.

(Effects of the Invention) As explained above, according to the present invention, the inputs to the variable coefficient multipliers of the ADFs are mutually orthogonalized between each ADF and within the ADF, and the root mean square values of each input are made equal. So,
The effect is that the convergence speed of the variable coefficients of each variable coefficient multiplier is fast.

The present invention is suitable for application to echo cancellers and the like.

[Brief explanation of the drawing]

Figure 1 (al is a block diagram showing the basic configuration of an embodiment of the present invention, Figure 1 (b) is the ADF-m (
A circuit diagram showing the configuration of m←M), Figure 1 fc) is shown in Figure 1 (
A circuit diagram showing the configuration of ADF-M in al, Figure 2 is AD
A block diagram for explaining the identification of an unknown system using F, Figure 3 shows A as an echo canceller that cancels echoes caused by acoustic coupling between a speaker and a microphone.
A diagram for explaining a remote conference system using DFTh,
Figure 4 is a circuit diagram showing the conventional ADF δ Sakaki Seikin, and Figure 5 (
a) is a circuit diagram showing the configuration of ADF-m (m-M) according to another embodiment of the present invention, and FIG. 5(b) is a circuit diagram showing the configuration of ADF-M according to another embodiment of the present invention. It is a diagram. l...Input terminal, 2...Output terminal, 3...Unknown system, 7...Adder, 8...Adder, 9...Adaptive digital filter (ADF), 10-1. 10-2
,... 10-M...input terminal, 11-1.11-2,...
・, 11-M...first output terminal, ρ-m, 22-M
...multiplier, η-m, Z3-M...first adder,
24-m, 24-M...third variable coefficient multiplier, 25-m, 25M...fourth variable coefficient multiplier, 26-m+26M...second variable coefficient multiplier, 27-m, 27-M...second adder, 4-
m, 28-M ---first variable coefficient multiplier, 2
9-m, 29-M... multiplier, 30-m, 30
- M...first adder, 31-m, 31-M--
first variable coefficient multiplier, 32-m; 32-M...Third variable coefficient multiplier, 33-m,
33-M...second variable coefficient multiplier, 34 m, 3
4 M... Fourth variable coefficient multiplier.

Claims (2)

[Claims] (1) Connect M basic sections (M is an integer greater than or equal to 1) in cascade, and each cascaded basic section up to (M-1) has an input terminal, a first output terminal, and a second output terminal. has an output terminal,
On the other hand, the M-th basic section has an input terminal and a first output terminal, the input terminal of the first basic section constitutes the signal input terminal of the adaptive digital filter, and each basic section from the second to the M-th An adaptive digital filter in which the input terminal of a section is connected to the second output terminal of the basic section immediately before it, and the sum of the signals obtained at the first output terminal of each basic section is the output of the adaptive digital filter. In the filter, a path from the input terminal of each of the M basic sections to the first output terminal is connected to a second-order cyclic digital filter and the input is the second-order cyclic digital filter.
It consists of a cascade connection with a first-order acyclic digital filter connected to a zero-order acyclic circuit of the next-order recursive digital filter, and A path leading to the second output terminal is configured by cascading the second order recursive digital filter and the second order non-recursive digital filter, and The cyclic digital filter has a signal u_m(k) input thereto multiplied by a coefficient R_m in a multiplier, and a signal u_m(k- 1) in a first adder, its output is multiplied by a variable coefficient T_m in a first variable coefficient multiplier, and the output g_m(k) is multiplied by a variable coefficient d_m(k) in a second variable coefficient multiplier. The signal d_m(k)・g_m(k) multiplied by the signal u_m(k)
) is multiplied by a variable coefficient S_m in a third variable coefficient multiplier, and the output f_m(k) is further multiplied by a variable coefficient c_m(k) in a fourth variable coefficient multiplier to generate a signal c_m(k)・f_m.
(k) in a second adder, the coefficient R_m is determined such that the signals f_(k) and g_m(k) are orthogonal, and the variable coefficient c_m(k), d_m(k)(m=1,2
, . are corrected at certain fixed time intervals so that S_m and T_
When modifying m, S_m・c_m(k) and T_m before modification
・S_m・c_m(k) and T after d_m(k) is corrected
An adaptive digital filter characterized in that c_m(k) and d_m(k) are corrected at each predetermined period of time, in addition to the above-described sequential correction, so that they are equal to _m·d_m(k), respectively. (2) Connect M basic sections (M is an integer greater than or equal to 1) in cascade, and each cascaded basic section up to (M-1) has an input terminal, a first output terminal, and a second output terminal. has an output terminal,
On the other hand, the M-th basic section has an input terminal and a first output terminal, the input terminal of the first basic section constitutes the signal input terminal of the adaptive digital filter, and each basic section from the second to the M-th An adaptive digital filter in which the input terminal of a section is connected to the second output terminal of the basic section immediately before it, and the sum of the signals obtained at the first output terminal of each basic section is the output of the adaptive digital filter. In the filter, a path from the input terminal of each of the M basic sections to the first output terminal is connected to a second-order cyclic digital filter and the input is the second-order cyclic digital filter.
It consists of a cascade connection with a first-order acyclic digital filter connected to a zero-order acyclic circuit of the next-order recursive digital filter, and A path leading to the second output terminal is configured by cascading the second-order recursive digital filter and the second-order non-recursive digital filter, and The cyclic digital filter uses the signal u_m(k) which is obtained by multiplying the signal u_m(k-1) one time before the signal u_m(k) input at time k by a coefficient ■_m in a multiplier. The first adder adds the sum, the first variable coefficient multiplier multiplies the output by a variable coefficient ■_m, and the second variable coefficient multiplier multiplies the output ■_m(k) by a variable coefficient c_m(k). The signal c_m(k)■_m(k
), the signal u_m(k-1) is multiplied by a variable coefficient ■_m in a third variable coefficient multiplier, and the output ■_m(k
) is multiplied by a variable coefficient d_m(k) in a fourth variable coefficient multiplier, and a signal d_(k)・■_m(k) is added in a second adder, and the coefficient ■_m is The signals ■_m(k) and ■_m(k)
and the variable coefficients c_m(k), d_m(k) (m=1, 2
, . The values are corrected at certain fixed intervals so that they become equal, and when this ■_m and ■_m are corrected, the pre-correction ■_m・c_m(k) and ■_m・d_m(k) become the post-correction ■_m・c_m. (k)
and■_m・d_m(k) separately from the above sequential correction so that they are equal to _m・d_m(k), respectively.
The adaptive digital filter is characterized in that the adaptive digital filter is corrected at the predetermined time interval.