JPS632300U

JPS632300U -

Info

Publication number: JPS632300U
Application number: JP9627186U
Authority: JP
Priority date: 1986-06-24
Filing date: 1986-06-24
Publication date: 1988-01-08

Description

[Brief explanation of the drawing]

第１図ａ，ｂは本実施例の読出し専用記憶装置
の回路図、第２図は本実施例の読出専用記憶装置
のタイムチヤート、第３図は従来の読出し専用記
憶装置の回路図である。１５……メモリセルマトリクス部、１６ａ〜１
６ｄ……ワード線、１７ａ〜１７ｄ……ビツト線
、１８……ローデコーダ、２１……アドレスプリ
チヤージ信号、２５……Ｐ型トランジスタ、２６
……プリチヤージ信号、２７ａ〜２７ｄ……ラツ
チ回路、２８ａ……Ｎ型トランジスタ、２９ａ〜
３１ａ……インバータ、３３ａ〜３３ｄ……出力
線。 1A and 1B are circuit diagrams of the read-only storage device of this embodiment, FIG. 2 is a time chart of the read-only storage device of this embodiment, and FIG. 3 is a circuit diagram of a conventional read-only storage device. . 15...Memory cell matrix section, 16a-1
6d... Word line, 17a-17d... Bit line, 18... Row decoder, 21... Address precharge signal, 25... P-type transistor, 26
...Precharge signal, 27a-27d...Latch circuit, 28a...N-type transistor, 29a-
31a...Inverter, 33a-33d...Output line.

Claims

[Scope of utility model registration request]

A memory cell matrix section in which memory cell sections are arranged in a matrix, a row decoder for selecting a word line of the memory cell matrix section, and a row decoder corresponding to each bit line of the memory cell matrix section. A plurality of latch circuits that collectively store data in all memory cell sections connected to a selected word line, and a column that selectively selects the plurality of latch circuits and reads out data stored in the latch circuits. A read-only storage device comprising: a decoder.