JPS632363A - Capacity film - Google Patents
Capacity filmInfo
- Publication number
- JPS632363A JPS632363A JP61145398A JP14539886A JPS632363A JP S632363 A JPS632363 A JP S632363A JP 61145398 A JP61145398 A JP 61145398A JP 14539886 A JP14539886 A JP 14539886A JP S632363 A JPS632363 A JP S632363A
- Authority
- JP
- Japan
- Prior art keywords
- film
- mixed
- region
- concentration
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000012528 membrane Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 9
- 229920005591 polysilicon Polymers 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 abstract description 4
- 239000000126 substance Substances 0.000 abstract description 3
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 abstract 2
- ZKATWMILCYLAPD-UHFFFAOYSA-N niobium pentoxide Chemical compound O=[Nb](=O)O[Nb](=O)=O ZKATWMILCYLAPD-UHFFFAOYSA-N 0.000 abstract 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 abstract 2
- 229910002113 barium titanate Inorganic materials 0.000 abstract 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 abstract 1
- 230000029305 taxis Effects 0.000 description 12
- 239000003990 capacitor Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 9
- 229910044991 metal oxide Inorganic materials 0.000 description 6
- 150000004706 metal oxides Chemical class 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000002894 organic compounds Chemical class 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 102220543423 26S proteasome non-ATPase regulatory subunit 10_L20S_mutation Human genes 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は容量膜に関し、特に半導体ダイナミックＲＡＭ
等の情報蓄積容量部の容量膜の構造に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a capacitor film, and particularly to a semiconductor dynamic RAM.
The present invention relates to the structure of a capacitive film of an information storage capacitor section such as the above.
ダイナミックＲＡ Ｍ （Ｒａｎｄｏｍ Ａｃｃｅｓｓ
Ｍｅｍｏｒｙ）のごとく、構成要素として容Ｉｋ金具備
した半導体装置においては、チップ中に占める容量の面
積を極力小さくすることが上記半導体装置の高密度化を
計る上で、！要である。容量の占める面積を小さくかつ
大きな容量値を得るために、従来、誘電材料としての比
訪電率の大きなＴａ酸化物、Ｔｉ酸化物、ｚｒ酸化物、
Ｈｆ酸化物などを用いることが試みられている。ところ
が、これら酸化物からなる絶縁膜はリーク電流が極めて
大きく、半導体装置の高密度化を計る目的から有望視さ
れながらも実用化に至っていない。この原因としては、
これら絶縁膜が形成された時点で多結晶の膜であったシ
、あるいは膜形成後時には非晶質であってもその後の低
温熱処理（６００’Ｃａ度）で多結晶の膜に変質するこ
とから、結晶粒界にそって電流カニ流れ易いためである
と推定される。従ってこれら膜のリーク電流を低減する
ためには、多結晶の膜になることを防止すればよいと言
える。Dynamic RAM (Random Access
In a semiconductor device that includes a capacitor as a component such as a memory, it is important to minimize the area occupied by the capacitor in the chip in order to increase the density of the semiconductor device. It is essential. In order to reduce the area occupied by the capacitor and obtain a large capacitance value, Ta oxide, Ti oxide, ZR oxide,
Attempts have been made to use Hf oxide and the like. However, insulating films made of these oxides have extremely large leakage currents, and although they are considered promising for the purpose of increasing the density of semiconductor devices, they have not been put into practical use. The cause of this is
These insulating films may be polycrystalline films at the time they are formed, or even if they are amorphous after film formation, they change into polycrystalline films by subsequent low-temperature heat treatment (600'Ca degrees). This is presumed to be because current tends to flow along grain boundaries. Therefore, in order to reduce the leakage current of these films, it is sufficient to prevent them from becoming polycrystalline films.
膜が多結晶になる原因としては、絶Ｒ膜形成時にあるい
はその後の熱処理の際に、絶縁膜とＳｉ基板とが反応し
絶縁膜中にＳｉが人、り界面が乱れるためと推定される
。かかる反応を防止するために、従来例えばＴａｘｅｓ
膜とＳｉ基板との間に非晶質のＳ ｉＯｚやＳｉＮｘ膜
をはさんで２層構造にした１）、Ｔａｘｅｓ膜中にＳｉ
等を混入することが検討されている。The reason why the film becomes polycrystalline is presumed to be that the insulating film and the Si substrate react with each other during the formation of the absolute R film or during the subsequent heat treatment, causing Si to enter the insulating film and disrupting the interface. In order to prevent such reactions, conventional methods such as Taxes
A two-layer structure is created by sandwiching an amorphous SiOz or SiNx film between the film and the Si substrate.
It is being considered to mix in
上述した従来のＴａｘｅｓ膜の多結晶化を防止する方法
は、以下のような欠点がある。Ｔａｘｅｓ膜とＳｉ基板
との間に非晶質の５ｉＯｚやＳｉＮｘ 膜をはさんで
２層構造する方法は、容量値が低減するという欠点があ
る。また、Ｔａｘｅｓ膜中にＳｔ等を混入させる方法は
、Ｓｉ基板との反応を防止するために混入量を１０％程
度にある必要があシ、この場合リーク電流は低減できる
が、容量値も大きく低減してしまう欠点がある。The conventional method for preventing polycrystalization of the Taxes film described above has the following drawbacks. The method of forming a two-layer structure by sandwiching an amorphous 5iOz or SiNx film between the Taxes film and the Si substrate has the disadvantage that the capacitance value is reduced. In addition, in the method of mixing St, etc. into the Taxes film, the amount of St or the like needs to be around 10% to prevent reaction with the Si substrate.In this case, leakage current can be reduced, but the capacitance value is also large. There is a drawback that it reduces
上述したように、容量値を低減させず、リーク；亀
電算を低減できる方法は開発されておらず、Ｔａｘｅｓ
膜未だ実用化されていない。As mentioned above, no method has been developed that can reduce leakage without reducing the capacitance value, and Taxes
The membrane has not yet been put into practical use.
本発明の目的は、リーク電流が小さくかつ容量値の大き
い容量膜を提供することにある。An object of the present invention is to provide a capacitive film with a small leakage current and a large capacitance value.
本発明の容量膜は、例えばＴＩＬ２０５膜中のＳｉ濃度
のプロファイルを変え、Ｓｉ基板との界面付近ではＳｉ
濃度を高くして膜の多結晶化を防いでリーク電流を低減
し、膜の内部ではＳｉ濃度を微量に抑えることで容量値
の低下を防ぎ、結果的にＴａｚＱｓ膜全体としてリーク
電流が小さく容量値の大きい膜としたものである。In the capacitive film of the present invention, for example, the Si concentration profile in the TIL205 film is changed, and near the interface with the Si substrate, Si
By increasing the concentration to prevent polycrystallization of the film and reducing leakage current, by suppressing the Si concentration to a very small amount inside the film, a decrease in capacitance value is prevented, resulting in a small leakage current and a high capacitance for the TazQs film as a whole. This is a film with a large value.
本発明の容量膜は、Ｔａ２ｅｓ、ＴｉＯ２，ＮｂｚＯｓ
。The capacitive film of the present invention includes Ta2es, TiO2, NbzOs
.
Ｈｆ０ｚ、Ｚｒ０ｚ、ＢＴｉＯｓＯうちいずれかにＳｔ
。St to any of Hf0z, Zr0z, BTiOsO
.
Ａ６．Ｇａ、Ｐ、Ｂのうちいずれかひとつの元素が含ま
れ、かつ、この元素濃度が膜の表面および裏面付近で高
く膜の内部で低く形成されていることを特徴とする。A6. It is characterized in that it contains any one of Ga, P, and B, and that the concentration of this element is high near the front and back surfaces of the film and low inside the film.
次に本発明る図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明を平面容量に適用したもので、容量の縦
断面構造を示す図である。基板１０１にシリコンを、容
量［１０２にＳｔ ｔ−微量含むＴａｘｅｓ膜を、電極
１０３にポリシリコンを用いて説明する。シリコン基板
はｐ型、ｎ型いずれの導電性を有する基板であってもよ
い。Ｔａｘｅｓ ｇの容量膜１０２の膜中には、Ｓｉが
微量含まれておシ、その濃度は第３図に示すようにシリ
コン基板１０１と容量膜１０２との界面（領域■）及び
容量膜１０２とポリシリコン電極１０３との界面付近（
領域１）で高くなり、膜内部（領域ｆｆ）で低濃度にな
りている。混入するＳｔの好ましい濃度は領域Ｉおよび
１では３〜３０％、領域■では０〜３％である。上述構
造のＴａ２ｅｓ膜の場合、シリコン基板１０１及びポリ
シリコン電極１０３から容量膜１０２へのＳｉの混入が
防止でき、界面に乱れが生じることを防ぎ、膜形成時や
後の熱処理によるＴａｘｅｓ膜の多結晶化を防止でき、
リーク電流を従来の１ｍＡ／Ｃ１１レベルからＩＱ−”
ＡΔレベルと小さくできる。また、Ｓｉ混入によるＴＪ
Ｌ２０Ｓ膜の容量値の低下も少ない。なお、Ｔａｘｅｓ
Ｍ以外のいっそう多結晶化しやすい膜の場合、多結晶
化を防げなくても混入Ｓｉによシ結晶粒界を埋め、リー
ク電流を低減できる効果も期待できる。なお、Ｓｉ濃度
の高い領域は約２０〜５０Ｘ程度設ければ充分である。FIG. 1 shows the application of the present invention to a planar capacitor, and is a diagram showing the vertical cross-sectional structure of the capacitor. A description will be given using silicon for the substrate 101, a Taxes film containing a small amount of St t- for the capacitor [102], and polysilicon for the electrode 103. The silicon substrate may be a substrate having either p-type or n-type conductivity. The capacitive film 102 of Taxes g contains a small amount of Si, and its concentration is at the interface (region ■) between the silicon substrate 101 and the capacitive film 102 and between the capacitive film 102 and the capacitive film 102, as shown in FIG. Near the interface with polysilicon electrode 103 (
The concentration is high in region 1) and low in the inside of the film (region ff). The preferred concentration of St to be mixed is 3 to 30% in regions I and 1, and 0 to 3% in region (2). In the case of the Ta2es film having the above structure, it is possible to prevent Si from entering the capacitor film 102 from the silicon substrate 101 and the polysilicon electrode 103, to prevent disturbances at the interface, and to prevent the Ta2es film from becoming contaminated during film formation or during subsequent heat treatment. Can prevent crystallization,
Reduced leakage current from conventional 1mA/C11 level to IQ-"
It can be made as small as AΔ level. In addition, TJ due to Si contamination
The decrease in the capacitance value of the L20S film is also small. In addition, Taxes
In the case of films other than M that are more likely to become polycrystalline, even if polycrystalization cannot be prevented, the effect of filling Si crystal grain boundaries with mixed Si and reducing leakage current can be expected. Note that it is sufficient to provide a region with a high Si concentration of about 20 to 50 times.
本発明の構造のＴａ２ｅｓ膜は、金属ＴａとＳｉとをス
パッタリング法等の手法で組成を変化させて形成した後
熱酸化するか、もしくは高周波スパッタ法あるいは化学
気相成長法（ＣＶＤ法）によシ混入するＳｉｆをコント
ロールして形成できるが、いずれの手法を選択するかは
自由である。また、Ｔａｘｅｓ代わりにＴｉ０ｚ、Ｎｂ
ｚＯｓ、Ｚｒ０ｚ。The Ta2es film having the structure of the present invention is formed by changing the composition of metal Ta and Si using a method such as sputtering, and then thermally oxidized, or by high-frequency sputtering or chemical vapor deposition (CVD). Although the Sif to be mixed in can be controlled and formed, it is free to select any method. Also, Ti0z, Nb instead of Taxes
zOs, Zr0z.
Ｈｆ０ｇ、ＢａＴｉ０ａ等の他の酸化物を用いても良く
、混入Ｓｉの代わシにＡＪ、Ｇｅ、Ｐ、Ｂ等の他の物質
を混入させてもＳｉと同等の効果を得る。Other oxides such as Hf0g and BaTi0a may be used, and even if other substances such as AJ, Ge, P, and B are mixed in place of Si, the same effect as that of Si can be obtained.
なお、ポリシリコンｚ杯ｔｏａはシリコン基板の内極と
なる電極であるが、その形成方法は目出である。この電
＆はポリシリコン層およびシリササイド層と順次積層し
たいわゆるポリサイド構造としても良い。Note that the polysilicon Z cup toa is an electrode that becomes the inner pole of the silicon substrate, but the method for forming it is a matter of special interest. This layer may have a so-called polycide structure in which a polysilicon layer and a silicide layer are sequentially laminated.
第２図は本発明を溝構造に適用したものであシ、縦断面
構造を示す図である。膜形成法は第１図で説明した方法
とほぼ同様であるが、溝内壁に均一な厚さを形成する必
要があることから、Ｓｉを混入したＴａｘｅｓ膜からな
る容：１ＪＩｌｉｌ１０２はＣＶＤ法によ多形成するの
が好ましい。この場合、例えばＴａ２’ｓの原料として
Ｔａの有機化合物等、また混入Ｓｔの原料としてＳｔの
有機化合物等を用いて、互いのキャリヤーガス流量を調
節することで容易に混入５ｔ−ｉを制御する手法が簡便
である。FIG. 2 is a diagram showing a vertical cross-sectional structure in which the present invention is applied to a groove structure. The film formation method is almost the same as the method explained in Fig. 1, but since it is necessary to form a uniform thickness on the inner wall of the groove, the film 1JIlil102, which is made of a Si-mixed Taxes film, is formed using the CVD method. Polymorphism is preferred. In this case, for example, by using an organic compound of Ta as a raw material for Ta2's and an organic compound of St as a raw material for mixed St, the mixed 5t-i can be easily controlled by adjusting the flow rate of each carrier gas. The method is simple.
また電極１０３は、ポリシリコンをＣＶＤ法で形成すれ
ば、溝内部に極めて容易に電極を埋めこむことができる
。本実施例によれば第１図の実施例と同様にリーク電流
を大幅に低減でき、容量値の大きい容量が得られる。Further, if the electrode 103 is formed of polysilicon by the CVD method, the electrode can be buried inside the groove very easily. According to this embodiment, as in the embodiment shown in FIG. 1, leakage current can be significantly reduced and a capacitor with a large capacitance value can be obtained.
なお、上記実施例では、Ｓｉ基板上に容量を形成したが
、電極基板上に形成してもなんらかまわない。In the above embodiment, the capacitor is formed on the Si substrate, but it may be formed on the electrode substrate.
また、上部電極にポリシリコンを用いたが、これに限定
されるものでな（、Ａｄ、Ｗ、Ｎｏ 等の金属を用い
てもよい。Further, although polysilicon is used for the upper electrode, the present invention is not limited to this; metals such as Ad, W, and No. 2 may also be used.
また、上記実施例において、ＴａｚＯｓｉとＳｔ基板と
の界面及びＴａｇ’ｓ膜とポリシリコン電極との界面の
２つの界面付近でＳｉ濃度が高くなってｂるが、必要に
応じてどちらか一方のみＳｉ濃度を高くするのも自由で
あシ、また２つの界面付近のＳｉ濃度を異なったＴａｚ
Ｏ５Ｍにするのも自由である。In addition, in the above example, the Si concentration increases near two interfaces: the interface between TazOsi and the St substrate, and the interface between the Tag's film and the polysilicon electrode, but only one of them can be used as needed. It is also possible to increase the Si concentration, and it is also possible to increase the Si concentration near the two interfaces.
You are also free to make it O5M.
以上説明したように本発明は、Ｔａｘｅｓ膜等の金属酸
化膜にＳｉ 、Ａｄ 、Ｇｅ 、Ｐ、Ｂ等のうちいずれ
かひとつの原素が含まれ、かつ画数物質の濃度が膜内部
では低く、膜の両端部では高くなるように形成すること
によシ、基板Ｓｔ等からのＴａ２ｅｓ膜等の金属酸化膜
への８１の混入を防止でき、金属酸化膜と基板Ｓｉ と
の界面及び金属酸化膜と電極との界面の乱れを防ぎ、そ
の結果、熱処理による金属酸化膜の多結晶化を防止する
効果がある。As explained above, in the present invention, a metal oxide film such as a Taxes film contains any one of Si, Ad, Ge, P, B, etc., and the concentration of the atom substance is low inside the film. By forming the film to be higher at both ends, it is possible to prevent 81 from being mixed into the metal oxide film such as the Ta2es film from the substrate St, etc., and the interface between the metal oxide film and the substrate Si and the metal oxide film can be prevented. This has the effect of preventing the interface between the metal oxide film and the electrode from being disturbed and, as a result, preventing the metal oxide film from becoming polycrystalline due to heat treatment.
また、膜内部の混入原素の濃度が低いため、混入原素に
よる容量膜の容量値の低下が小さくできるという効果も
ある。Furthermore, since the concentration of the mixed element inside the film is low, there is an effect that the decrease in the capacitance value of the capacitive film due to the mixed element can be reduced.
以上のように本発明の構造を用いれば、リーク電流を低
減でき、かつ、容量値の低減が小さく、高誘電率材料の
性質をいかした容量膜を形成することが可能である。As described above, by using the structure of the present invention, it is possible to reduce leakage current, reduce the reduction in capacitance value to a small extent, and form a capacitive film that takes advantage of the properties of a high dielectric constant material.
第１図は本発明の第１の実施例の縦断面図、第２図は本
発明の第２の実施例の縦断面図、第３図は本発明による
Ｓｔを含むＴａｘｅｓ膜中のＳｉ濃度の深さプロファイ
ル図である。
１０１・・・・・・基板、１０２・・・・・・容量膜、
１０３・・・・・・電極。
旦Ｌ ′島
代理人 弁理士 内 原 ａ（・。FIG. 1 is a longitudinal sectional view of the first embodiment of the present invention, FIG. 2 is a longitudinal sectional view of the second embodiment of the present invention, and FIG. 3 is the Si concentration in the Taxes film containing St according to the present invention. FIG. 101...substrate, 102...capacitive film,
103... Electrode. Tan L 'Shima's agent Patent attorney Uchihara A (.
Claims (1)
Ｏ＿２、ＺｒＯ＿２、ＢＴｉＯ＿３のうちのいずれかに
、Ｓｉ、Ａｅ、Ｇｅ、Ｐ、Ｂのうちいずれかひとつの元
素が含まれ、かつ、当該元素濃度が膜の表面および裏面
付近で高く膜の内部で低く形成されていることを特徴と
する容量膜。Ta_2O_5, TiO_2, Nb_2O_5, Hf
Any one of O_2, ZrO_2, and BTiO_3 contains one of Si, Ae, Ge, P, and B, and the concentration of the element is high near the front and back surfaces of the film and inside the film. A capacitive membrane characterized by being formed low.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61145398A JPS632363A (en) | 1986-06-20 | 1986-06-20 | Capacity film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61145398A JPS632363A (en) | 1986-06-20 | 1986-06-20 | Capacity film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS632363A true JPS632363A (en) | 1988-01-07 |
| JPH0553069B2 JPH0553069B2 (en) | 1993-08-09 |
Family
ID=15384335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61145398A Granted JPS632363A (en) | 1986-06-20 | 1986-06-20 | Capacity film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS632363A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5143861A (en) * | 1989-03-06 | 1992-09-01 | Sgs-Thomson Microelectronics, Inc. | Method making a dynamic random access memory cell with a tungsten plug |
| US6267470B1 (en) * | 1996-01-11 | 2001-07-31 | Canon Kabushiki Kaisha | Ink jet head structure having MOS transistors for power supply, and head substrate, ink jet cartridge, and ink jet apparatus having the same |
| JP2001237424A (en) * | 1999-12-24 | 2001-08-31 | Hynix Semiconductor Inc | Method for manufacturing semiconductor device to which gate dielectric film is applied |
| JP2002519865A (en) * | 1998-06-30 | 2002-07-02 | ラム リサーチ コーポレーション | ULSIMOS with high dielectric constant gate insulator |
| JP2008252118A (en) * | 1998-03-12 | 2008-10-16 | Lucent Technol Inc | Electronic component with doped metal oxide dielectric material and process for making electronic component with doped metal oxide dielectric material |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5861634A (en) * | 1981-10-09 | 1983-04-12 | Fujitsu Ltd | Manufacture of dielectric layer for semiconductor device |
| JPS61156865A (en) * | 1984-12-28 | 1986-07-16 | Nec Corp | Semiconductor device |
-
1986
- 1986-06-20 JP JP61145398A patent/JPS632363A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5861634A (en) * | 1981-10-09 | 1983-04-12 | Fujitsu Ltd | Manufacture of dielectric layer for semiconductor device |
| JPS61156865A (en) * | 1984-12-28 | 1986-07-16 | Nec Corp | Semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5143861A (en) * | 1989-03-06 | 1992-09-01 | Sgs-Thomson Microelectronics, Inc. | Method making a dynamic random access memory cell with a tungsten plug |
| US6267470B1 (en) * | 1996-01-11 | 2001-07-31 | Canon Kabushiki Kaisha | Ink jet head structure having MOS transistors for power supply, and head substrate, ink jet cartridge, and ink jet apparatus having the same |
| JP2008252118A (en) * | 1998-03-12 | 2008-10-16 | Lucent Technol Inc | Electronic component with doped metal oxide dielectric material and process for making electronic component with doped metal oxide dielectric material |
| JP2013093589A (en) * | 1998-03-12 | 2013-05-16 | Alcatel-Lucent Usa Inc | Individual element including dielectric materials or integrated circuit device including semiconductor device |
| JP2002519865A (en) * | 1998-06-30 | 2002-07-02 | ラム リサーチ コーポレーション | ULSIMOS with high dielectric constant gate insulator |
| JP2001237424A (en) * | 1999-12-24 | 2001-08-31 | Hynix Semiconductor Inc | Method for manufacturing semiconductor device to which gate dielectric film is applied |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0553069B2 (en) | 1993-08-09 |
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