JPS63244251A - Controller for reset signal of system bus - Google Patents

Abstract

PURPOSE:To sufficiently satisfy the iPSB bus specifications and to effectively generate a reset signal by controlling output timing by means of a microcontroller to turn on/off a reset signal RST*, DCLOW* for the system. CONSTITUTION:To following two are provided: the microcomputer 1 that controls its own timing corresponding to a reset request signal or an interruption request and request for the outputting of a reset signal RST* and DCLOW* on corresponding iPSB, and a reset control circuit 2 that controls the turning on/off of the RST* and the DCLOW*. As a result, at the time of generating an output request for a cold reset or warm reset signal, a reset signal in accordance with the specifications of the system bus can be controlled, then outputted easily with simple circuit constitution. Also, a reset request from an external constituent element through the system bus and can cope with a resetting request by means of a remote signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a system bus reset signal control device that controls the output of a plurality of reset signals on a system bus of an information processing system.

(Conventional technology) As a system bus for information processing systems, multipath ■
(Product name: MULTIBUSII) When using the i PSB bus (Product name: Intel Parallel System Path), the reset signals R8T' and [)CLOW' on this path are specified as signals. However, there has been no clear hardware for the i-control circuit.

(Problem to be Solved by the Invention) As described above, in the past, there were regulations regarding the system reset signals R8T' and DCLOW'' on the i PSB bus of multipath ■, but the control circuit was not clearly defined in hardware. The problem was that it did not exist.

SUMMARY OF THE INVENTION In view of these problems, it is an object of the present invention to provide a reset signal t11 control device that fully satisfies the iPSB bus standard and can effectively generate a reset signal.

(Structure of the Invention) (Means for Solving the Problems) In order to achieve such an object, the present invention provides a cold or warm reset in response to a reset request command via the multipath i PSB bus. An iPSB interface circuit that generates a request signal, a reset interrupt circuit that requests an interrupt for each reset using a remote signal, etc., and a power supply start-up circuit that outputs a cold reset request signal during a voltage unstable period when the power is turned on. a microcontroller that requests the output of the reset signals R8T' and DCLOW' on the corresponding IPSB while measuring the timing according to each of the reset request signals or interrupt requests, and this output request or the power supply. R8T@ and D are activated by a cold reset request from the startup reset circuit or a Ti source status signal from the power supply section
A system bus reset signal m, which is equipped with a reset control circuit that controls on/off of CLOW'.
*Invented the i-device.

(Function) If the system bus reset signal control device has such a configuration, a cold reset request is issued by the reset circuit at power-on, the reset control circuit is activated, and the DCL O corresponding to the cold reset is activated.
It is possible to turn both the W'' and R8T' signals on and off according to the iPSB bus specifications, and also to enable reset request commands and remote reset requests via the iPSB bus when the power is turned off or when the power is turned down. It is possible to control the output of both of the above-mentioned signals or only the R8T'' signal corresponding to the warm reset as appropriate in response to occurrences of the above-mentioned signals or the occurrence of a system stall.

(Embodiment) FIG. 1 is a schematic block diagram of a system bus reset signal control device as an embodiment to which the present invention is applied. 1 is a microcontroller, 2 is a reset control circuit including a driver to the JPSB bus, 3 is a power-on reset circuit, 4 is a reset interrupt circuit, 5 is a system power supply section, and 6 is an iPS8 bus interface. , performs data transfer between the microcontroller 1 and other components (agents) on the iPSB bus.

Further, the second FIJ is a timing chart showing the output states of the system reset signals DCLOW' and R8T'' on the iPSB bus, in which (a) represents a cold reset, and (b) represents a warm reset. Note that tl, t2, and t3 in the figure indicate the time width that satisfies the minimum signal holding time determined by the + pss bus standard. Also, "*" indicates negative logic, and each signal in the figure OFF when high level ()-1rG)-1>, low level (LOW)
When it is in the on state, it is on.

Next, the operation will be explained. First, at power-on, when the system power supply unit 5 is started, during the period when the power supply voltage is unstable, the power-on reset circuit 3 sends recall reset request signals C and J to each reset control circuit. 2 and the microcontroller 1. When the signal C becomes valid (high level), the reset control circuit 2 unconditionally outputs the signal 81 (DCLOW') and the signal 82 (R8
T") is turned on (low level). When the power supply voltage becomes stable, the signal E from the power supply unit 5 becomes high level, and thereby the signal B1 (DCLOW") is turned off (high level). That is, DCLOW'=C"AND E (* indicates negative logic). Also, the reset signal 82 (R3T") is kept in the on state by the reset control circuit 2 by the boat data A output from the microcontroller 1. has been done. The microcontroller 1 is reset for several milliseconds by the output signal J of the power-on reset circuit 3, and during this period continues to output the boat data A to keep R8T" on. Thereafter, an initialization sequence is performed, and Wait until DCLOW@ turns off, [
After holding the R8T' signal (B2) for a period of 2, the data A causes the reset control circuit 2 to turn off the R8T' signal (B2).

When the power is turned off or turned on, the power supply unit 5 outputs a signal E at a low level as a warning signal. In response to this signal E, the reset control circuit 2 sends DCLOW' signal @(
81) and sends a signal to the critical interrupt circuit 4@
D is set high and output to generate an interrupt signal K to the microcontroller 1. As shown in FIG. 2(a), the microcontroller 1 which received the interrupt in this way sends the R8T signal to the R8T via the boat data A1 reset control circuit 2 after a period of approximately tl from the time when DCLOW is turned on.
” (B2) Turn on the signal.

A reset request command from an external agent via the iPSB bus is received by the iPSB bus interface circuit 6 and sent to the microcontroller 1. The microcontroller 1 recognizes this command, determines whether it is a cold or warm reset, and controls the boat data A so that the data changes as shown in FIG. 2 (a> or (b).
) at the timing of DCLOW” and (or)
The R8T0 signal is output to the reset control circuit 2.

Furthermore, when a reset is requested by a remote signal, an interrupt signal K is sent to the microcontroller 1 through the reset interrupt circuit 4 along with the distinction between cold and warm reset, and the output of both reset signals is controlled by 11 in the same way as in the case of the above command. Ru.

Roughly speaking, even when a system stall occurs, by setting a reset register (not shown) in the microcontroller 1, both reset signals I and II t can be set in the same way.
An is output.

In this way, the system reset signal R8 is controlled by the microcontroller 1 while controlling the output timing.
T'' and DCLOW' can be turned on and off in accordance with the iPSB bus regulations.

〔Effect of the invention〕

As explained above, the system bus reset signal control device to which the present invention is applied can easily generate a reset signal corresponding to the standard of the system bus when a cold reset or warm reset signal output request occurs. With a simple circuit configuration, it is possible to control output.

It is also possible to respond to reset requests from external components via the system bus and reset requests by remote signals.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a system bus reset signal IiI1wlJ device according to an embodiment to which the present invention is applied, and FIG. 2 is an output timing chart of the system reset signal on the same side.

Claims (1)

[Claims] (1) A cold reset request command that initializes the entire system including memory clearing via the system bus of the information processing system, or a warm reset request command that initializes system operations but does not include memory clearing. a system bus interface circuit that generates a cold or warm reset request signal in response to the power supply; a power supply start-up reset circuit that generates the cold reset request signal during an unstable period when the power is turned on; a reset interrupt circuit that receives a requesting remote signal and generates an interrupt request signal for each reset, and receives the cold or warm reset request signal or the interrupt request signal and controls the timing, A microcontroller that requests the output of multiple reset signals on the system bus corresponding to a cold or warm reset, and a microcontroller that requests the output of multiple reset signals on the system bus corresponding to a cold or warm reset, and a microcontroller that requests the output of multiple reset signals on the system bus corresponding to a cold or warm reset, and a reset control circuit that receives an information signal caused by the power supply operating state, such as a shutdown notice signal, and turns on and off a plurality of reset signals on the system bus; In response to power-off, reset requests via the system bus, remote reset requests, etc., multiple reset signals on the corresponding system bus are turned on and off.
A system bus reset signal control device that performs control while measuring timing.