JPS63266830A - Flattening method for surface - Google Patents
Flattening method for surfaceInfo
- Publication number
- JPS63266830A JPS63266830A JP9989787A JP9989787A JPS63266830A JP S63266830 A JPS63266830 A JP S63266830A JP 9989787 A JP9989787 A JP 9989787A JP 9989787 A JP9989787 A JP 9989787A JP S63266830 A JPS63266830 A JP S63266830A
- Authority
- JP
- Japan
- Prior art keywords
- sio2
- silicon
- polishing
- silicon film
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 27
- 239000010703 silicon Substances 0.000 claims abstract description 27
- 238000005498 polishing Methods 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 50
- 229910052681 coesite Inorganic materials 0.000 abstract description 25
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 25
- 239000000377 silicon dioxide Substances 0.000 abstract description 25
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 25
- 229910052682 stishovite Inorganic materials 0.000 abstract description 25
- 229910052905 tridymite Inorganic materials 0.000 abstract description 25
- 239000010410 layer Substances 0.000 abstract description 8
- 238000001312 dry etching Methods 0.000 abstract description 5
- YCIMNLLNPGFGHC-UHFFFAOYSA-N catechol Chemical compound OC1=CC=CC=C1O YCIMNLLNPGFGHC-UHFFFAOYSA-N 0.000 abstract description 4
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 abstract description 2
- 239000007864 aqueous solution Substances 0.000 abstract description 2
- 239000011229 interlayer Substances 0.000 abstract description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract description 2
- 229920000728 polyester Polymers 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000003082 abrasive agent Substances 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Formation Of Insulating Films (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野」
本発明は半導体素子の製造プロセスにおけるSiO2の
表面平坦化方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for planarizing the surface of SiO2 in the manufacturing process of semiconductor devices.
[従来の技術]
半導体素子、集積回路の製造工程においては、これらを
構成する個々のトランジスタ、配線などの工程によって
そのデバイス層の表面には必ず凹凸を生ずる。この凹凸
はさらにその後の多層配線などの工程にとって大ぎな障
害となっている。また、能動層をSiO2などの絶縁層
を介して多層に積層した構造、いわゆる三次元回路素子
の作製においても、このSiO2の表面に凹凸があるこ
とはその上の能動層形成に不都合でおる。[Prior Art] In the manufacturing process of semiconductor devices and integrated circuits, irregularities are inevitably created on the surface of the device layer due to the process of forming individual transistors, wiring, etc. that constitute these devices. This unevenness further becomes a major hindrance to subsequent processes such as multilayer wiring. Further, even in the production of a so-called three-dimensional circuit element having a structure in which active layers are laminated in multiple layers with insulating layers such as SiO2 interposed therebetween, the presence of irregularities on the surface of this SiO2 is inconvenient for forming the active layer thereon.
従来から行われている表面の平坦化方法としては流動性
のある有機膜をスピン塗布した後、等速ドライエツチン
グをする方法、およびポリシングによる方法がある。Conventional surface planarization methods include spin coating a fluid organic film followed by constant speed dry etching, and polishing.
[発明が解決しようとする問題点]
しかしながらスピン塗布と等速ドライエツチングによる
方法では、第一段階での流動性有機膜の平坦化が問題で
ある。すなわち、流動性が必すしも十分でないために表
面に凹凸が残ったり、あるいはドライエツチング前の焼
きしめ熱処理時には必ず膜の収縮がおこるが、5102
の凹部では凸部に比へて膜が厚いため収縮量も多く、結
果として初めに残った凹凸か拡大されるなどの問題点が
あった。[Problems to be Solved by the Invention] However, in the method using spin coating and constant speed dry etching, flattening of the fluid organic film in the first step is a problem. In other words, because the fluidity is not necessarily sufficient, unevenness remains on the surface, or shrinkage of the film always occurs during the baking heat treatment before dry etching.
Since the film is thicker in the recessed portions than in the convex portions, the amount of shrinkage is greater, and as a result, the remaining unevenness is enlarged.
一方、ポリシングによる方法では、局所的に見た平坦性
は極めて良好となるが、大口径全面にわたる均一性はウ
ェハのそり、厚さの不均一などから問題があった。On the other hand, in the polishing method, the flatness seen locally is extremely good, but there are problems with uniformity over the entire large diameter surface due to warpage of the wafer, uneven thickness, etc.
本発明は以上)ホべたような従来の問題点を解消するた
めになされたもので、大口径ウェハであってもウェハ仝
体にわたり良好な平坦面を得ることのできる表面平坦化
方法を提供することを目的とする。The present invention has been made in order to solve the above-mentioned conventional problems, and provides a surface flattening method that can obtain a good flat surface over the entire wafer even for large diameter wafers. The purpose is to
[問題点を解決するための手段]
本発明は、表面に凹凸が形成されたSiO2上にシリコ
ン膜をS!02上の凹凸の段差以上の厚さに堆積する工
程と、前記シリコン膜を選択ポリシングし、前記510
2の凸部をストッパーとする平坦面を形成する工程と、
前記SiO2とシリコンの等速エツチングを行ってSi
O2の平坦面を形成する工程とを有してなることを特徴
とする表面平坦化方法である。[Means for Solving the Problems] The present invention provides S! a silicon film on SiO2 with an uneven surface. A step of depositing the silicon film to a thickness equal to or greater than the level difference between the concavities and convexities on the 510
forming a flat surface using the convex portion of No. 2 as a stopper;
By performing the uniform etching of SiO2 and silicon,
This is a surface flattening method characterized by comprising a step of forming an O2 flat surface.
[作用]
本発明で重要な点は第一段階での平坦化(SiO2上の
凹部を充填して平坦化する段階)においてSiO2の凹
部の充填にシリコンを用いること、およびこの平坦化工
程に続いてSiO2をストッパーとするシリコンの選択
ポリシングを用いることである。選択ポリシングとはシ
リコンと研摩液との化学反応とこれに続くその反応生成
物の機械的除去作用を利用したもので、シリコンに対し
ては例えば10卯/hの研摩速度を持つが、SiO2に
対しては、上述の化学反応が生じないため実質的に研摩
速度はゼロとなるような物質を用いる方法である。この
結果、選択ポリシングの段階での平坦性および大ロ径つ
ェハ内均−性は極めて良好となり、その後のシリコンと
SiO2の等速エツチングによって最終的な8102表
面の平坦化が実現される。[Function] An important point in the present invention is that silicon is used to fill the recesses in SiO2 in the first step of planarization (the step of filling the recesses on SiO2 and flattening it), and that following this planarization step, silicon is used to fill the recesses in SiO2. The method is to use selective polishing of silicon using SiO2 as a stopper. Selective polishing is a method that utilizes a chemical reaction between silicon and a polishing solution followed by mechanical removal of the reaction product. For silicon, the polishing speed is, for example, 10 m/h, but for SiO2, On the other hand, there is a method of using a substance that does not cause the above-mentioned chemical reaction, so that the polishing rate becomes substantially zero. As a result, the flatness and uniformity within the large-diameter wafer at the stage of selective polishing are extremely good, and the subsequent uniform etching of silicon and SiO2 achieves final planarization of the 8102 surface.
[実施例] 以下、本発明の実施例を図面を用いて詳細に説明する。[Example] Embodiments of the present invention will be described in detail below with reference to the drawings.
第1図は本発明の方法の一実施例を示す工程図である。FIG. 1 is a process diagram showing an embodiment of the method of the present invention.
第1図(a)はシリコン基板1の上にデバイス層2が形
成され、その上にデバイス保護および層間絶縁膜となる
SiO23が形成された状態である。デバイス層の表面
は凹凸形状となるため、SiO23の上面もこれを反映
して凹凸形状となる。FIG. 1(a) shows a state in which a device layer 2 is formed on a silicon substrate 1, and SiO 23 serving as a device protection and interlayer insulating film is formed thereon. Since the surface of the device layer has an uneven shape, the upper surface of the SiO 23 also has an uneven shape reflecting this.
第1図(b)はSiO23にシリコン膜4をLPCVD
法で形成した状態を示し、このシリコン膜4の上面には
やはり凹凸がある。第1図(C)は前記シリコン膜4上
を選択ポリシングすることによりSiO23の凸部がス
トッパーとなって自動的にポリシングが停止し、SiO
2の凹部にシリコン膜が残り表面が平坦となった状態を
示す。本実施例では、この選択ポリシングは、ウェハを
支持板にワックスで固定し、ポリエステル製のポリシン
グパッドと、エチレンジアミン・ピロカテコール水溶液
によって行った。この時いわゆる研摩材は一切用いなか
った。次いで、シリコンとSiO2に対するエツチング
速度の等しくなるドライエツチングを行うことにより、
第1図(d)に示すようなSiO2の平坦化が完了する
。Figure 1(b) shows a silicon film 4 formed on SiO23 by LPCVD.
The upper surface of the silicon film 4 is shown to be formed by the method, and the upper surface of the silicon film 4 is uneven. FIG. 1(C) shows that by selectively polishing the silicon film 4, the convex portion of the SiO23 acts as a stopper and the polishing is automatically stopped.
This shows a state in which the silicon film remains in the recessed portion of No. 2 and the surface is flat. In this example, the selective polishing was performed by fixing the wafer to a support plate with wax and using a polyester polishing pad and an aqueous solution of ethylenediamine/pyrocatechol. At this time, no abrasive material was used. Next, by performing dry etching to equalize the etching speed for silicon and SiO2,
Planarization of SiO2 as shown in FIG. 1(d) is completed.
なお、第1図(a)の状態でのSiO23の凹凸の段差
は1,5廓であったが、最終的なSiO23の凹凸の段
差は500八であり、かつ4インヂウエハの全面にわた
り良好な均一性が得られた。Note that in the state shown in Figure 1(a), the level difference in the unevenness of SiO23 was 1.5 degrees, but the final level difference in the unevenness of SiO23 was 5008 degrees, and it was well uniform over the entire surface of the 4-inch wafer. I got sex.
[発明の効果]
以上説明したように、本発明の方法によれば、SiO2
の表面平坦化において、SiO2の凹部にシリコンを埋
めて表面を平坦とする第一段階の平坦化の完全性が極め
て優れている。また、この工程にはSiO2の凸部をス
トッパーとする選択ポリシングによる自動的なポリシン
グ停止機構を有しているから、大口径ウェハ内の均一性
も良い。この結果、ウェハ全面にわたって均一なSiO
2平坦面を得ることができる。[Effect of the invention] As explained above, according to the method of the present invention, SiO2
In surface planarization, the first step of flattening the surface by filling silicon into the recesses of SiO2 is extremely complete. Further, since this process has an automatic polishing stop mechanism by selective polishing using the convex portion of SiO2 as a stopper, the uniformity within the large diameter wafer is also good. As a result, uniform SiO is formed over the entire wafer surface.
2 flat surfaces can be obtained.
第1図は本発明の方法の一実施例を示す工程図である。 FIG. 1 is a process diagram showing an embodiment of the method of the present invention.
Claims (1)
膜をSiO_2上の凹凸の段差以上の厚さに堆積する工
程と、前記シリコン膜を選択ポリシングし、前記SiO
_2の凸部をストッパーとする平坦面を形成する工程と
、前記SiO_2とシリコンの等速エッチングを行つて
SiO_2の平坦面を形成する工程とを有してなること
を特徴とする表面平坦化方法。(1) A step of depositing a silicon film on the SiO_2 whose surface is uneven, to a thickness equal to or greater than the level difference of the unevenness on the SiO_2, and selectively polishing the silicon film,
A surface flattening method characterized by comprising a step of forming a flat surface using the convex portion of _2 as a stopper, and a step of etching the SiO_2 and silicon at a constant rate to form a flat surface of SiO_2. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9989787A JPS63266830A (en) | 1987-04-24 | 1987-04-24 | Flattening method for surface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9989787A JPS63266830A (en) | 1987-04-24 | 1987-04-24 | Flattening method for surface |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63266830A true JPS63266830A (en) | 1988-11-02 |
Family
ID=14259561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9989787A Pending JPS63266830A (en) | 1987-04-24 | 1987-04-24 | Flattening method for surface |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63266830A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5214001A (en) * | 1990-01-18 | 1993-05-25 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device having planar single crystal semiconductor surface |
| US5356513A (en) * | 1993-04-22 | 1994-10-18 | International Business Machines Corporation | Polishstop planarization method and structure |
| US5445996A (en) * | 1992-05-26 | 1995-08-29 | Kabushiki Kaisha Toshiba | Method for planarizing a semiconductor device having a amorphous layer |
| US5795495A (en) * | 1994-04-25 | 1998-08-18 | Micron Technology, Inc. | Method of chemical mechanical polishing for dielectric layers |
-
1987
- 1987-04-24 JP JP9989787A patent/JPS63266830A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5214001A (en) * | 1990-01-18 | 1993-05-25 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device having planar single crystal semiconductor surface |
| US5445996A (en) * | 1992-05-26 | 1995-08-29 | Kabushiki Kaisha Toshiba | Method for planarizing a semiconductor device having a amorphous layer |
| US5914275A (en) * | 1992-05-26 | 1999-06-22 | Kabushiki Kaisha Toshiba | Polishing apparatus and method for planarizing layer on a semiconductor wafer |
| US5948205A (en) * | 1992-05-26 | 1999-09-07 | Kabushiki Kaisha Toshiba | Polishing apparatus and method for planarizing layer on a semiconductor wafer |
| US5356513A (en) * | 1993-04-22 | 1994-10-18 | International Business Machines Corporation | Polishstop planarization method and structure |
| US5510652A (en) * | 1993-04-22 | 1996-04-23 | International Business Machines Corporation | Polishstop planarization structure |
| US5795495A (en) * | 1994-04-25 | 1998-08-18 | Micron Technology, Inc. | Method of chemical mechanical polishing for dielectric layers |
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