JPS63287266A - Sink chip clamp circuit - Google Patents

Abstract

PURPOSE:To attain stable clamp by providing a limit circuit leading a clamp pulse only in the timing when the clamp pulses are generated consecutively. CONSTITUTION:A clamp pulse is inputted to a shift register 6 receiving a timing pulse given to an AD conversion circuit 1 as a shift pulse, and an output of each stage of the shift register is given to an OR gate 7 and also given to a switching means 4 as a switching control input to an integration circuit. Thus, the clamp pulse is formed and introduced only when the clamp pulse having a pulse width over a period corresponding to the number of stages of the shift registers 6 is generated and more stable clamping is attained in comparison with the constitution where a negative peak voltage of noise is used as a clamp level.

Description

[Detailed description of the invention] (6) Industrial application fields The present invention relates to improvements in sync tip clamp circuits.

(Concerning the configuration that performs sync-tegg clang in the previous stage when AD converting a conventional technology video signal, please refer to Magazine 1 Transistor Technology' November 1986 issue 366-3, published by CQ Publishing Co., Ltd.)
It is also disclosed on page 67.

FIG. 4 shows the circuit configuration of a conventional sync tip clamp circuit. As is clear from this figure, the input video signal is input to the positive terminal of the first operational amplifier (2), and its output is A.
It is input to the D converter (1).

When the value of the AD converted data becomes O (ie, the reference level), a low level output is generated via the gate (5).

The exchanging means (4) is switched to this low level output. This switching means (4) inputs the HI level output to form a discharge circuit of red impedance, and inputs the A level output to form a low impedance photoelectric circuit. That is, a negative power supply is connected to the negative terminal of the second operational amplifier (2), which constitutes a part of the integrating circuit, through a second resistor (R2), which normally has high impedance.
The photoelectric current 'i!L?Fi' of the integrating capacitor (C1) is discharged at a low speed, and the integrating capacitor (C1) is rapidly discharged through the low impedance first resistor (R1) only when an a-level gate output is generated. It's photoelectric.

The output of this second operational amplifier (3) is the output of the first operational amplifier (
2) Connected to the negative terminal? @Sa1, As a result, the sink chimp level is clamped. In the configuration described above, the operating waveforms are shown in Figure 5. ) occurs during the period when the output (jL) is below the reference level, and every time the gate output occurs, the output (C) of 3) is caused to drop to the photoelectric voltage by the reference level. The reference level eventually converges to the sync tip level to realize sync tip clamp.

el Problems to be Solved by the Invention However, with the above-mentioned configuration, if the area near the sink tip A is flat as shown in FIG. Although this is possible, if the sink chimp level fluctuates due to noise as shown in Figure 7, the fund level (φ
The Cla 7 circuit operates so that H) matches.

Therefore, the video signal level changes depending on the noise of the thin edge lag accompanied by fluctuations, making the clamp operation unstable. The present invention is characterized in that, in the sync chip clamp circuit that clamps the video signal based on the integral output level, a limiting circuit is added to derive the clamp pulse only at the timing when the clamp pulse is continuously generated.

10. 9. If Ln is used in the present invention, the sink clock quanging is performed at a level such that the gate circuit output is continuously formed.

(f) Example The present invention will be described below with reference to illustrative embodiments.

First, the first embodiment shown in diagram Xg1 utilizes a combination of a shift register (6) and an OR circuit (7) as a limiting means in the conventional circuit described above.

νU, in this embodiment, a gate (5
), a large number of ramp pulses as shown in FIG. 2(a) are derived for the video signal as shown in FIG. 2 near the sync tip of the video signal. A wide clamp pulse is derived during a stable period where the noise level is low. This embodiment is characterized in that the ramp is performed only when this wide clamp pulse is generated. Therefore, the clamp pulse is input to the shift register (6) which inputs the timing pulse input to the AD conversion circuit [1] as a shift pulse. Although the shift register is shown in three stages in FIG. 1, the number of stages may be set as appropriate depending on the noise level state. The output of each stage of this shift register is input to an OR gate (7) and then input to a switching means (4) as a switching control input of an integrating circuit. Therefore, if L in this embodiment, shift register (6)
A rung pulse is formed and derived as shown in FIG. 2 (dl) only when a clamp pulse having a period longer than the number of stages is generated. Therefore, as shown in FIG. In this embodiment, it is possible to set a clamp voltage (ep) that is slightly lower than the ideal lamp voltage (ao).
) Compared to the configuration where the level is Kkukumpu, a stable rung is possible.

7? , FIG. 3 shows a second embodiment of the invention. In the second embodiment, the present invention is applied to a circuit that derives the clamp output without AD conversion, and the third operational amplifier (9), which functions as a comparator when deriving the clamp pulse, is connected to the clamp output and the reference output. Comparing t-levels. The clamp pulse derived as a result has a waveform as shown in FIG. 2B, similar to the first embodiment. In this example,
This clamp pulse is input to the analog delay element (8), and a number of outputs are derived from the intermediate connection point F, and these outputs are input to the OR gate (force). From this, the output shown in Figure 2 Comparison] is derived.

As a result, the switching means (4) is activated only during the clamp pulse generation period which is longer than the period corresponding to the delay M of the delay element.
forms a photoelectric path.

(G) Based on the effects of the invention, the JfL of the present invention approximates the clamp level to the ideal level, and then detects a period with a small noise level by adjusting the clamp pulse width, and during that period, the sync chip clamp is fully applied. Since it is contained, it becomes possible to make a stable lamp.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing the first embodiment of the present invention, Fig. 2 is a waveform diagram of the same main part, Fig. 3 is a circuit diagram of the second embodiment, Fig. 4 is a conventional circuit diagram, and Fig. 5 is a circuit diagram showing the first embodiment of the present invention. The figure is a waveform diagram of the same main part, 'ig6 figure and M
FIG. 7 is an explanatory diagram showing the relationship between the video signal and the clamp level, FIG. 6 is a diagram showing the relationship when the noise level is small, and FIG. M7 is a diagram showing the relationship when the noise level is large. (5)...Clamp pulse generation circuit (gate circuit,
(C1)...fi capacitor, (4)...switching means.

Claims (1)

[Claims] (1) A clamp pulse generation circuit that generates a clamp pulse when the clamp output falls below a reference level, an integrating circuit that performs integration based on the clamp pulse, and a clamp level of the video signal based on the output level of the integrating circuit. In the sync tip clamp circuit, the sync-chip clamp circuit is configured to include a specified clamp circuit, and a limiting circuit that derives the clamp pulse only at the timing when the clamp pulse is continuously generated between the clamp pulse generating circuit and the integrating circuit. A sink tip clamp circuit characterized by arranging.