JPS63299545A - Routine data detecting circuit - Google Patents

Abstract

PURPOSE:To obtain a routine data detecting circuit which can detect the routine data in a simple constitution by providing two shift registers and two arithmetic circuits. CONSTITUTION:A 1st shift register 12 receives the routine data sent repetitively in a prescribed pattern at its input terminal and stores the minimum unit of the repeating cycle. A 1st arithmetic circuit 13 discriminates whether the data pattern stored in the register 12 is equal to a prescribed one or not and outputs this discriminated data in the binary 0 or 1. Furthermore a 2nd shift register 14 has the same number of stages equal to the repeating frequency of the minimum unit of the routine data and receives the supply of the output of the circuit 13. While a 2nd arithmetic circuit 15 obtains the output that discriminated whether the data on the prescribed number of stages stored in the register 14 are all equal to each other or not. In such a constitution, it is just required for the first stage part to perform the bit precessing for detection of a minimum pattern and also for the rear stage part to perform the arithmetic processing of the bits in the same number as the repeating frequency. As a result, the number of component elements can be decreased.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) This invention relates to a fixed data detection method that detects data sent in a fixed format, such as a clock run-in signal of a teletext broadcasting signal. Regarding circuits.

(Prior Art) In a teletext receiving device, character data is multiplexed and transmitted during a part of the vertical synchronization period of a television signal. In order to detect whether or not this character data is multiplexed, a predetermined horizontal line within the vertical synchronization period is sampled.
It is sufficient to detect whether or not a character multiplex signal (character packet) exists in this horizontal line in a predetermined format.

In order to detect this, first, a clock run-in signal, which serves as a reference phase for obtaining clock synchronization, is multiplexed in a predetermined format at the beginning of the character multiplexed signal, so the presence of this clock run-in signal is necessary. Just check.

A conventional circuit for detecting the clock run-in signal is configured as shown in FIG. The input terminal 101 is supplied with a horizontal line signal on which a character multiplex signal is superimposed. Of course, this signal has been converted from analog to digital at the previous stage. The signal at the input terminal 101 is guided to a shift register 102 having a data storage capacity of the same data length as the clock run-in signal. The clock run-in signal is 4
When binarized at an interval of 15 fsc, the result is usually 010101.
..., and with all bits stored in the shift register 102, the arithmetic circuits 103, 102, .
104, 105, and 106, it is determined whether the pattern is a predetermined pattern or not.

The determination result is output to the output terminal 107 as "0" when a predetermined pattern is detected, and as "1" otherwise.

Figure 4 shows the circuit in Figure 3 in more detail.
Corresponding parts are given the same reference numerals.

Arithmetic circuits 103 to 106 each include inverters INL and IN2 for making each bit output of the shift register the same sign when the clock run-in signal is stored in a predetermined pattern, the output of the inverter, and the output of the remaining bits. It is constructed of a NAND circuit NAND that performs logical operations. Further, the arithmetic circuit 107 includes each arithmetic circuit 10
It is constituted by an OR circuit OR which takes the logical sum of the outputs of 3 to 106.

(Problems to be Solved by the Invention) According to the conventional correction data or clock run-in signal detection circuit described above, the same number of arithmetic circuits as the data length of the clock run-in signal is required. For example, as shown in figure m4, in the case of a signal in which a 1010" pattern is sent four times in succession, the arithmetic circuit requires 58 elements.If the length of the clock run-in signal is increased, the length of the clock run-in signal can be increased. The number of elements increases, leading to an increase in price.

SUMMARY OF THE INVENTION An object of the present invention is to provide a fixed data detection circuit that can detect a pattern of fixed data such as a clock run-in signal with a simple configuration.

[Structure of the Invention] (Means for Solving the Problems) This invention provides a first input terminal in which fixed data repeatedly sent in a predetermined pattern is supplied to an input terminal, and which stores at least the minimum unit of the repetition period. and this first register.
Discrimination data that determines whether the data pattern stored in the register is a predetermined pattern is set to 0 or 1.
a first arithmetic circuit that outputs a value; a second shift register to which the output of the arithmetic circuit is supplied and whose number of stages is at least the same as the number of repetitions of the minimum unit of the fixed form data; and a second shift register that is stored in the second shift register. and a second arithmetic circuit that obtains an output that determines whether or not the data in each predetermined stage are all the same value.

(Function) With the above means, the minimum unit pattern is detected by the first shift register and the first arithmetic circuit in the previous stage, and whether or not the patterns of each minimum unit are all the same is detected by the second stage in the subsequent stage. It is detected by the shift register and the second arithmetic circuit. Therefore, the first stage only needs to perform bit processing to detect the minimum pattern, and the second stage only needs to perform arithmetic processing on at least as many bits as the number of repetitions, making it possible to significantly reduce the number of components compared to the conventional method. become.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which a horizontal line signal on which a character multiplex signal is superimposed is supplied to an input terminal 11 after being analog-to-digital converted at a previous stage. This signal is
For example, the fixed data is supplied to a shift register 12 having a number of bit stages corresponding to at least one period (minimum unit) of the clock run-in signal repetition period. This shift register 1
Each bit of 2 is led to an arithmetic circuit 13. When this arithmetic circuit 13 detects that the minimum unit pattern is a predetermined pattern, it outputs "0"; otherwise, it outputs "0".
Outputs 1".

The output of the arithmetic circuit 13 is supplied to a shift register 14 having the same number of stages as the number of consecutive repetitions of the regular data. Each bit output of this shift register 14 is supplied to an arithmetic circuit 15. This arithmetic circuit 15 includes a shift register 14
"1" only when each bit of is the same value "1"
The detection of the clock run-in signal is outputted to the output terminal 16 as a determination output. In other cases, "0" is output.

Therefore, according to the above-mentioned detection circuit, there is no need to temporarily store all bits of the clock run-in signal in a register and discriminate them all by an arithmetic circuit as in the conventional case, and the configuration can be significantly simplified.

FIG. 2 is an example showing the circuit of FIG. 1 in more detail.

Therefore, corresponding parts are given the same reference numerals. The shift register 12 at the front stage has, for example, four stages, and the shift register 14 at the rear stage has thirteen stages. The fixed form data is assumed to be 0101 repeated four times. The arithmetic circuit 13 is composed of inverters INI and IN2 connected every other bit to each bit of the shift register 12, and a NAND circuit NAND into which the outputs of these inverters IN1 and IN2 and the outputs of the remaining bits are introduced. .

In addition, the arithmetic circuit 15 operates in an OR circuit 01? into which a predetermined bit of the shift register 14, that is, a bit corresponding to four cycles, is introduced. It is made up of. According to the detection circuit configured in this way, a pattern of 4 cycles of regular data with 4 bits as one cycle is determined, and if this pattern is a predetermined pattern (repetition of 0101...), the output terminal 16 is determined. An output of "O" is obtained from this, and an output of "1" is obtained for other cases.

Let us consider the conditions for minimizing the number of elements in the circuit shown in FIG.

First, in order to judge the 0101 pattern four times, if the number of stages of the front stage shift register is n stages and the number of output lines of the rear stage shift register is m, then n Xm-16 Calculating the number of elements in the operation section is as follows . If the number of elements is M, then M − (nX2) + (n/2 X2) + (mX2
) +2-3n+2m+2 -3n+ (32/n) +2 Since n must be a positive even number to minimize M,
Considering this, it becomes n-4, which is the value that can be realized with the minimum number of elements. While the conventional circuit shown in FIG. 4 requires 58 elements, the present invention can be realized with 22 elements, that is, less than half the number of elements. The following values were used to calculate the number of elements: NAND circuit...number of inputs x 2, inverter...2, AND circuit, OR circuit...number of inputs x 2+2, shift register...number of stages x 10゜[Effect of the Invention] As explained above, according to the present invention, a fixed-form data detection circuit that can detect fixed-form data in a simple manner (with one component) is proposed.
%can do.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific example of the circuit in FIG. 1, FIG. 3 is a diagram showing a conventional clock run-in signal detection circuit, and FIG. The figure is a circuit diagram showing a specific example of the circuit of FIG. 3. 12.14...Shift register, 13.15...Arithmetic circuit. Figure 2 16″

Claims (1)

[Claims] Fixed-form data that is repeatedly sent in a predetermined pattern is supplied to an input terminal, and includes a first register that stores at least the minimum unit of the repetition period; a first arithmetic circuit that outputs discrimination data that determines whether or not the data pattern is a predetermined pattern as a binary value of 0 or 1; and an output of the arithmetic circuit is supplied, and at least the minimum unit of the fixed data A second shift register having the same number of stages as the number of repetitions, and a second arithmetic circuit that obtains an output that determines whether data in a predetermined stage stored in the second shift register are all the same value. A fixed-form data detection circuit featuring: