JPH0454744A - Signaling detector - Google Patents

Abstract

PURPOSE:To reduce the processing time to detect a state change by detecting a state change of a signaling data of each channel for a period different from the type of the signaling data. CONSTITUTION:An input data from a data input terminal 1 is inputted to a shift register circuit 61 of an extraction section 6. The circuit 61 extracts a signaling bit from the input data and gives it to latch circuits 63-66. Each of the latch circuits 63-66 latches the signaling bit relating to its own circuit sent from the circuit 61 in response to a signal addressed to its own circuit in output signals from a counter circuit 62. A selector circuit 71 selects one of the latch circuits 63-66 and writes the signaling bit outputted from the selected latch to a memory 73 by a type of each signaling bit. A change according to types of each signaling bit in the signaling bits of each channel stored in the memory 73 is monitored to detect a state change in each signaling bit of each channel.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to adaptive quantized differential pulse code modulation (ADPC).
M) This relates to a signaling detection device that detects the state of signaling inserted into a signal.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional signaling detection device. In the figure, 1 is a data input terminal to which input data having multiple channels and multiple signaling bits of different signaling types are inserted for each channel is input, and 2 is the input terminal to which the signaling enable signal is input. This is the enable input terminal.

Reference numeral 3 denotes an extraction unit which extracts each signaling bit from each channel of the input data inputted to the data input terminal 1 based on the signaling enable signal inputted to the enable input terminal 2.

4 is a storage unit equipped with a memory for storing each signaling bit of each channel extracted by this extraction unit 3;
Reference numeral 5 denotes a detection unit that monitors each signaling bit stored in the memory of the storage unit 4 on a channel-by-channel basis to detect changes in the signaling state of each channel.

Next, the operation will be explained. Input data is input from the data input terminal 1, and a signaling enable signal is input from the enable input terminal 2, respectively, to the extraction unit 3. When the signaling enable signal is active, the extraction unit 3 extracts the signaling bit from the input data and outputs it to the storage unit 4.

The storage section 4 writes the signaling bits extracted by the extraction section 3 into a built-in memory for each channel of input data. FIG. 5 is an explanatory diagram showing the storage state of the signaling bits in the memory of the storage unit 4, and in the same figure, there is a case where signaling bits of four types of signaling A to D are inserted into each channel of input data. is exemplified.

In this manner, changes in the signaling bits of each channel stored in the storage section 4 are monitored for each channel by signals from the detection section 5.

That is, the detection unit 5 sets the signaling bit of each channel to 1.
Each signaling A compared to that before multi-frame
-D state changes are detected for each channel. Therefore,
The signaling of A to D will be monitored in the same period on each channel.

Here, such a signaling detection device is disclosed in, for example, Japanese Patent Laid-Open No. 1-115235.

Problem to be solved by the invention C] Since the conventional signaling detection device is configured as described above, when signaling bits of multiple types of signaling are inserted for each channel, it is difficult to detect a change in the state of the signaling bit. However, all types of signaling are processed together in the same cycle for each channel, and both signaling that changes less frequently and signaling that changes more frequently must be processed in the same cycle, and Since even the signaling bits that do not have the same value are subject to processing, there is a problem in that the processing takes a lot of time.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a signaling detection device that can shorten the processing time for detecting a change in the state of a signaling bit.

[Means to solve the problem]

In the signaling detection device according to the present invention, the signaling bits extracted by the extraction unit are classified by type of signaling and stored in the storage unit, and the detection unit monitors the signaling bits accumulated in the storage unit. This is performed at a cycle corresponding to the type, and has a function of detecting changes in the signaling state of each channel for each type of signaling.

E-effect] The detection unit in the present invention monitors the signaling bits stored in the storage unit for each type of signaling at a cycle corresponding to the frequency of change of the signaling bits for each type of signaling, and detects the difference in the signaling. By detecting changes in the signaling state of each channel at different cycles depending on the type, the monitoring cycle for signaling bits that change little is lengthened and the processing time for detecting state changes is shortened.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is a data input terminal, and 2 is an enable input terminal, which are the same as those of the conventional device.

61 shifts the input data input from this data input terminal 1, and outputs signaling bits of four types of signaling A to D from each channel of the input data according to the signaling enable signal input from the enable input terminal 2. It is a shift register circuit. 62 is a counter circuit that counts the signaling enable signals and generates a signal for latching the signaling bits of each signaling A to D.

63 to 66 are provided corresponding to each of the signaling bits A to D, and among the signaling bits sent from the shift register circuit 61, those of the corresponding signaling bits A to D are processed in response to the output signal of the counter circuit 62. This is a latch circuit that latches. 6 are these shift register circuits 61,
This is an extraction section composed of a counter circuit 62 and latch circuits 63 to 66, and corresponds to that shown by reference numeral 3 in FIG.

71 is a selector circuit that selects one of the signaling bits output by each of the latch circuits 63 to 66, and 72 is a counter circuit that generates a selection signal for this selector circuit 71. A memory 73 stores the signaling bits selected by the selector circuit 71 for each signaling type A to D. 7 is a selector circuit 71, a counter circuit 72, and a memory 7.
3, which corresponds to the storage section designated by reference numeral 4 in FIG.

8 is a detection unit corresponding to the detection unit shown with reference numeral 5 in FIG. This differs from the conventional one in that it has a function of detecting changes in the signaling status of each channel for each type A to D.

Next, the operation will be explained. Input data is input from the data input terminal 1, and a signaling enable signal is input from the enable input terminal 2 to the shift register circuit 61 of the extraction section 6, respectively. When the input signaling enable signal is active, the shift register circuit 61 extracts the signaling bit from the input data and supplies it to the latch circuit 6.
3 to 66.

On the other hand, the counter circuit 62 counts the signaling enable signals and outputs each type of signaling A-D.
Generates a signal to latch the signaling bit of. Each of the latch circuits 63 to 66 latches a corresponding one of the signaling bits sent from the shift register circuit 61 in response to the one addressed to it among the output signals from the counter circuit 62. For example, the latch circuit 63 latches the signaling bit of signaling A, the latch circuit 64 latches the signaling bit of signaling B, the latch circuit 65 latches the signaling bit of signaling C, and the latch circuit 66 latches the signaling bit of signaling D.

Each of the latch circuits 63 to 66 outputs the signaling bits latched in units of 8 bits to the selector circuit 71 of the storage section 7. Here, the counter circuit 72 of the storage section 7 counts the signal from the counter circuit 62 of the extraction section 6, and when the signaling bits are each input to the selector circuit 71 in units of 8 bits, the signal is output to the selector circuit 71. Outputs selection signal.

The selector circuit 71 selects one of the latch circuits 63 to 66 in accordance with this selection signal, and writes the 8-bit signaling bits output from the latch circuits into the memory 73 for each signaling type A to D.

FIG. 2 is an explanatory diagram showing the storage state of signaling bits in this memory 73. The figure shows input data 1 to 3.
A case is illustrated in which the signaling bits of each channel of 0 are grouped by signaling type A to D and stored in separate words.

The signaling bits of each channel stored in the memory 73 of the storage unit 7 in this manner are monitored for changes for each signaling type A to D by signals from the detection unit 8. That is, the detection unit 8 compares the signaling bit of each channel with the previous one at a predetermined period determined for each signaling type A to D. The detection unit 8 thereby detects changes in the state of each signaling in each channel at different cycles corresponding to the frequency of change in the signaling bits for each of the signaling types A to D.

Here, FIG. 3 is a time chart showing the period of the signal sent by the detection section 8 to the memory 73 of the storage section 7 in order to detect a state change of each signaling bit. According to the illustrated example, the respective state changes of the signaling A are detected in the fastest period "a", the respective state changes of the signaling B are detected in the subsequent period "b", and the timings of the signaling C and D are shifted from each other in the slowest period "a". C" or d" is detected.

In the above embodiments, a case has been described in which a memory is used to store each signaling bit, but register files, flip-flops, etc. may also be used, and the same effects as in the above embodiments can be achieved.

【Effect of the invention〕

As described above, according to the present invention, the signaling bits are classified according to the type of signaling and stored in the storage section, and are monitored at a cycle according to the frequency of change of the signaling bits for each type of signaling. Since the configuration is configured to detect changes in the signaling state of each channel at different cycles, it is possible to lengthen the monitoring cycle for signaling bits that change little, reducing the processing time for detecting state changes. This has the effect of providing a signaling detection device that can perform

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a signaling detection device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the storage state of signaling bits in the storage section, and FIG. 3 is a diagram showing the storage state of signaling bits sent from the detection section to the storage section. FIG. 4 is a block diagram showing a conventional signaling detection device, and FIG. 5 is an explanatory diagram showing the storage state of signaling bits in its storage unit. 6 is an extraction section, 7 is a storage section, and 8 is a detection section. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] an extraction unit that receives input data in which a plurality of signaling bits of different signaling types are inserted for each channel, and extracts the signaling bits for each signaling type from each channel; a storage unit that stores the signaling bits classified by the type of signaling, and a storage unit that monitors the signaling bits stored in the storage unit at a cycle corresponding to the type of signaling, and stores the signaling bits for each type of signaling. and a detection unit that detects a change in the signaling state of each channel.