JPS63316092A - Display circuit with hard copy data memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a display circuit with hardcopy data memory;
In particular, the present invention relates to a display circuit suitable for displaying graphs and characters on a CRT (Cathode Ray Tubes) and making a hard copy of a microcomputer system or the like.

[Conventional technology]

Conventionally, this type of device has C only for character display and for graph display.
Most of the time, RT display circuits were used, but recently, as the number of characters displayed in graphs has increased, and the display characters have been changed to kanji, a CRT display circuit that combines the functions of character display and graph display has become necessary from the viewpoint of display speed. It has become.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology has the problem that a hard copy cannot be taken at high speed because the character display pattern is not written on the image memory due to high-speed rewriting of one display.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display circuit with a hard copy data memory capable of high-speed hard copying in addition to a high-speed rewriting function for one display.

[Means for solving problems]

The above purpose is to provide a logic operation circuit that performs logic operations between two types of parallel data output from a character generator and graph display data memory, a memory that stores the output data of this logic operation circuit, and a write address of this memory. The printer is equipped with an address control circuit that controls the read address, and when a hard copy is required, this is achieved by sending the data on the memory to the printer.

[Effect]

When displaying on a raster scan CRT, two sets of parallel data from the graph image memory and character generator are output at regular intervals in accordance with the movement of the raster scan, and after being logically summed for each bit, the data is transferred to a shift register. The signal is input to the parallel input terminal of the computer, latched, converted into a serial signal, and output as a CRT image signal. Therefore, data input to the parallel input terminal of the shift register at a constant cycle is written into the memory whose address is updated at every constant cycle at the timing when the data is latched by the shift register. As a result, while the CRT raster scans one screen, one screen of the composite pattern of graphs and characters is written into the memory.

〔Example〕

The present invention will be described in detail below with reference to the embodiment shown in FIG. 1 and FIGS. 2 to 4.

FIG. 1 is a circuit diagram showing an embodiment of a display circuit with hard copy data memory of the present invention. In Fig. 1, 1 is a memory for graph display data, 2 is a character generator, a logic operation circuit 3 inputs 8-bit output data from these two and outputs OR data, and an output from the logic operation circuit 3. A tri-state buffer 5 buffers the output signal from the logic operation circuit 3, and the output signal of the tri-state buffer 5 is input to the CRT display circuit, which is composed of a shift register 4 which converts the signal into serial data by a signal to DotCL. Memory 6 for input and Memory 6
a tri-state buffer 7 that buffers the output signal of and outputs the data to the outside; an address counter 8 that controls the address data of the memory 6; and a flip-flop 9 that sets the mode of write operation and read operation of the memory 6. is built in and operates in the following order.

2 to 4 are timing diagrams showing the operation of the signals in the circuit of FIG. 1. As shown in FIG.
When it reaches the 0" level, the Q signal output of the flip-flop 9 becomes the gt O" level.

The gate of the tri-state buffer 5 is opened, and the logic operation circuit 3 inputs the OR signal of the output of the graph display data memory 1 and the output signal from the character generator 2 to the memory 6. Also, the Q signal output of the flip-flop 9 becomes "1" level, and the vertical synchronizing signal VSYNC of the L knee CRT (7) is input to the clear signal input terminal (CLR) of the address counter 8, and the raster scan of the CRT is started. Immediately before the start, the output value of address counter 8 is “0”.
”, and the signal output from flip-flop 9 is 1.
” level, the W signal as shown in FIG. The same data as the 8 bits of data is written to the address counter 8. Then, the S/τ signal shown in FIG. ) is input, and 1 is added to the output value of the address counter 8 at the timing of the rising edge of the S/L signal.As a result, the address at address 1 in the memory 6 is latched into the shift register 4 and the value that was displayed on the CRT last time is added to the output value of the address counter 8. Subsequently, 8 bits of data to be displayed is written. This operation continues until the output value of the address counter 8 reaches the maximum value set inside the address counter 8. As a result, the data is sequentially latched into the shift register 4 and Dot in figure 2
The data that is output as serial data to the CL at the rising timing of the signal and displayed on the CRT is written every time the address of the memory 6 is sequentially increased, and the image data displayed on the CRT is stored in the memory 6 as it is. . The maximum value set in address counter 8 is CR
The address value necessary to memorize the data displayed for the T-screen is set, and when the output value of the address counter 8 reaches this value, the ■RRY signal output terminal of the address counter 8 goes to the ``O'' level. becomes flip flop 9
inverts the output of , changing from write mode to read mode.

In the read mode, as shown in Figure 4, the D
The data input to o=D7 is the upper address write signal ASETH and the lower address write signal ASETL.
The start address to be read from the memory 6 is set in the address counter 8 by this. Next, read control signal DRE
When AD reaches the Pa0'' level, the data written from the memory 6 to the address output by the address counter 8 is output to DO''D7. This allows the contents of the memory 6 to be read from the outside. Also, since the Q output of the flip-flop 9 changes to the ``1'' level so that the DREAD signal is input to the CLK terminal of the address counter 8, each time the DREAD signal changes from ``0'' to ``1''. The output of address counter 8 is incremented by 1.As a result, each time data is read, DREAI
) By simply changing the signal once from 110"' to "1'° level, the contents of the memory 6 to which the address has been added by 1 are outputted to Do"Dv.

According to this embodiment, when an image pattern for one screen is memorized simply by sending a signal specifying the write mode, it is automatically terminated and set to a readable state, so there is no need to perform complicated control from the outside. In addition, in the read operation, by simply setting the start address once, the address advances automatically from the next time without specifying the address, and data can be read out one after another.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to inexpensively store an image pattern displayed on a CRT in memory in the time it takes for the CRT display circuit to display one screen, which is 1/2 that of a conventional high-speed hard copy device. This has the effect of realizing a hard copy system at a price of ~115. In addition, compared to the conventional technology in which display data is stored after being converted to a serial signal, the response speed of the circuit required to capture the signal is ↓/parallel data length before serial data conversion, In the case of 8 bits, the effect is that a circuit with a response speed of 178 times can perform memory operations at the same speed.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of a display circuit with hard copy data memory of the present invention, and FIGS. 2 to 4 are timing diagrams showing the operation of signals in the circuit of FIG. 1. 1... Memory for graph display data, 2... Character generator, 3... Logical operation circuit, 4... Shift register, 5, 7... Tri-state buffer, 6
...Memory, 8...Address counter, 9...Flip-flop. Book II! 1

Claims (1)

[Claims] 1. A logical operation that performs a logical operation between two sets of parallel data outputs from the character generator and the graph display data memory in a display circuit that synthesizes and displays output data from the character generator and the graph display data memory. 1. A display circuit with a hard copy data memory, comprising a circuit, a memory for storing output data of the logic operation circuit, and an address control circuit for controlling write addresses and read addresses of the memory.