JPS6334316Y2 - - Google Patents
Info
- Publication number
- JPS6334316Y2 JPS6334316Y2 JP1982009294U JP929482U JPS6334316Y2 JP S6334316 Y2 JPS6334316 Y2 JP S6334316Y2 JP 1982009294 U JP1982009294 U JP 1982009294U JP 929482 U JP929482 U JP 929482U JP S6334316 Y2 JPS6334316 Y2 JP S6334316Y2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- copper foil
- electronic component
- die bond
- grounding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Die Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982009294U JPS58111992U (ja) | 1982-01-25 | 1982-01-25 | 固体電子部品のシ−ルド構造 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982009294U JPS58111992U (ja) | 1982-01-25 | 1982-01-25 | 固体電子部品のシ−ルド構造 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58111992U JPS58111992U (ja) | 1983-07-30 |
| JPS6334316Y2 true JPS6334316Y2 (2) | 1988-09-12 |
Family
ID=30021947
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1982009294U Granted JPS58111992U (ja) | 1982-01-25 | 1982-01-25 | 固体電子部品のシ−ルド構造 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58111992U (2) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60180852A (ja) * | 1984-02-28 | 1985-09-14 | Kyocera Corp | 熱印刷装置 |
-
1982
- 1982-01-25 JP JP1982009294U patent/JPS58111992U/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58111992U (ja) | 1983-07-30 |
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