JPS6339936B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a scan-in-out control circuit, and in particular, to a scan-in-out control circuit that maintains the same scan-in-out operation even if the number of flip-flop FFs in a scan chain changes. Scan scan that allows you to perform
Regarding the in/out control circuit.

(b) Conventional technology and problems In the scan-in-out system, 1.
When the number of FFs constituting a scan chain changes, it has conventionally been necessary to recognize the number and connection order of FFs in a circuit that controls scan-in/out operations, and to change the number of clocks to be shifted. For this reason, the control circuit has the complexity of having a table or the like every time the number of FFs in the scan chain changes. In addition, as a partial improvement, there is a method in which the circuit that performs the scan control can always operate in a single manner by controlling the shift clock or the connection form of the scan chain. A dummy FF used only for in/out is required, or (2)
There were problems such as the fact that the FFs constituting the scan chain were divided into exactly the same number to form a small scan chain, which had to be controlled independently, resulting in an increase in circuit size and complexity.

(C) Purpose of the Invention The present invention solves the above problems and makes it possible to maintain the same scan-in/out control operation with a simple configuration even if the number of FFs forming the scan chain changes. It is intended to.

(d) Structure of the Invention In order to achieve the above object, the present invention provides a method for connecting n flip-flops in series for maintenance, diagnosis, etc. of a logic circuit including n flip-flops that are subject to scan-in-out control. A shift register consisting of m flip-flops is connected to the scan chain to form a scan loop, and by applying a required number of shift clocks, input/output control of this data via the shift register is performed. In the in-out system, there is provided a counting means for counting the shift clocks, a means for suppressing the shift clocks to the flip-flops in the logic circuit by means of a control signal based on the count value of the counting means, and a means for inhibiting the shift clocks to the flip-flops in the logic circuit by means of the control signal. means for disconnecting the scan chain consisting of a shift register consisting of m flip-flops, and means for configuring a scan loop of only the shift register according to the control signal, Even when there are no m×k flip-flops, the same number of shift clocks are generated as when there are n flip-flops, and scan-in/out control is performed in the same manner as the input/output control operation. It is characterized by

(e) Embodiments of the Invention FIG. 1 is a circuit example of a conventional general scan-in-out system. In the diagram, 1-1 to 1-
6 is a flip-flop to be diagnosed, 2-1 to 2-
2 is a shift register for scan-in/out control, and 3 is a shift clock generation circuit. In this way, by connecting the scan chain consisting of n FFs and the shift register consisting of m FFs in a loop and applying the required number of shift clocks, scan-in of any FF among n bits is possible. An out action is performed.

Next, FIG. 2 shows a circuit according to an embodiment of the present invention.

In FIG. 2, 10-1 to 10-4 are flip-flops to be diagnosed, 11-1 to 11-2 are shift registers for scan-in-out control, and 1
2 is a shift clock generation circuit, 13 is a shift clock counting circuit, 14 to 16 are AND gates, 17
is an OR gate, and 18 and 19 are inverters.
In FIG. 2, among n FFs to be diagnosed, m
The case where ×k FFs are missing is shown. FIG. 3 is a time chart of the circuit of FIG. 2.

Before starting the scan-in-out operation, the shift clock counting circuit 13 is cleared. In this state, until n ₂ shift clocks are applied, the switch is connected to the scan chain as before.
The contents of FF are shifted. n _Second counting circuit 1
Signal A from 3 is turned on. Thereafter, the signal A remains on until m×k shift clocks are applied, and among the FFs in the scan chain, the states of n ₁ and n ₂ FFs do not change because the shift clocks are inhibited. On the other hand, m FF11-
1 to 11-2 are only m closed scan chains, and after m×k shift clocks are applied, they are in the same state as before.

Furthermore, when n ₁ +m shift clocks are applied in this state, all FFs return to their original states. As described above, the shift clock generation circuit 12
Then, in the scan chain, m×k FFs
There is no need to recognize that it does not exist. Further, a dummy FF only for performing the scan operation is not required, and the additional circuit is simple.

(F) Effects of the Invention According to the present invention, it is possible to cope with changes in the number of FFs to be diagnosed in a scan chain with a simple configuration, and the economic advantage is great.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a circuit example of a conventional general scan-in-out system, FIG. 2 is a diagram showing a circuit of an embodiment according to the present invention, and FIG. 3 is a time chart of the embodiment. In Fig. 2, 10-1 to 10-4 are flip-flops to be diagnosed, and 11 to 12 are scan flip-flops.
A shift register for in/out control, 12 a shift clock generation circuit, and 13 a shift clock counting circuit.

Claims (1)

[Claims] 1 n subject to scan-in-out control
For maintenance, diagnosis, etc. of a logic circuit containing m flip-flops, a shift register consisting of m flip-flops is connected to a scan chain in which the flip-flops are connected in series to form a scan loop, and the necessary number of shift clocks are connected. In the scan-in-out system, the input/output of data via the shift register is controlled by applying a clock signal, a counting means for counting the shift clock in the logic circuit, and control based on the count value of the counting means. means for inhibiting shift clocks to the n flip-flops in the logic circuit by a signal; and means for inhibiting shift clocks to the n flip-flops in the logic circuit by the control signal;
and means for configuring a scan loop of only the shift register by means of the control signal. Even when n flip-flops do not exist, the same number of shift clocks are generated as when there are n flip-flops, and scan-in-out control is performed in the same manner as input/output control operation. In/out control circuit.