JPS6347330B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing an alignment mark that enables improvement of alignment accuracy without changing conventional processes in a photolithography process of a semiconductor device manufacturing process. .

(Prior Art) When performing alignment work, alignment marks are covered with an etched film and a resist film.

The visibility of the edge of the alignment mark is a major factor influencing alignment accuracy, and the higher the mark visibility, the higher the alignment accuracy.

One way to improve the visibility of this alignment mark is to reduce the thickness of the thin film (etched film, resist film) on the alignment mark.

In general, it has been confirmed that as the resist film on the alignment mark becomes thinner, the visibility of the alignment mark improves, and alignment accuracy improves accordingly.

Figure 1 shows an example of this, with the horizontal axis showing the resist thickness and the vertical axis showing alignment variations (variations in alignment accuracy between the wafer alignment mark and the mask substrate). A polysilicon film is used as the film to be etched on the 8000Å oxide film with alignment marks.
This is data obtained when alignment was performed using a reduction projection aligner when a resist film of 10,000 Å was coated at three levels.

As mentioned above, the resist film thickness on the alignment mark is determined by the process in each step (problems such as step coverage of the pattern taking into account the resist film reduction during development and etching), and conventional alignment Mark (method)
It has been impossible to reduce the thickness of the resist film only on the alignment marks by adjusting parameters (resist spinner rotation speed, displacement) in resist film coating.

Figures 2a to 2c are diagrams showing the steps of a conventional alignment mark manufacturing method.As an example, an example is shown in which alignment marks are created by a photolithography process using polysilicon used as a gate and wiring material. It shows.

First, as shown in FIG.
A polysilicon film 23 (2000~
5000Å).

Next, as shown in FIG. 2b, alignment marks 23 are created by photolithography. In this case, on the alignment mark 23,
A resist film 25 {for example, AZ1350,
AZ1470 (trade name of Hoechst)} was formed as shown in FIG. 2c.

If this resist film 25 has a thickness of 15000 Å other than the portion above the alignment mark 23, then
The thickness 26 of the resist film 25 on the alignment mark 23 is 12,000 to 14,000 Å, and there is not that much difference in film thickness between the two.

The alignment mark 23 on the base film 21 has a surface of, for example, about 30 to 40μ square, and is generally placed around the chip. Silicon is the material of the gate electrode, and therefore the thickness of the alignment mark 23 is, for example, about 4500 Å.

However, the thickness of the resist film 25 is generally approximately
When applied at about 15000Å, when applying the resist,
Conventionally, it is difficult to reduce the thickness 26 of the resist film 25 over the alignment mark 23 region to less than 12,000 to 14,000 Å.

Therefore, the edges of the alignment mark 23 region become unclear, and the accuracy of mark alignment cannot be improved.

(Purpose of the Invention) This invention was made to eliminate the above-mentioned conventional drawbacks, and it is possible to reduce the thickness of the resist film only on the alignment mark area without increasing the number of steps, thereby improving the visibility of the alignment mark. An object of the present invention is to provide a method for manufacturing an alignment mark that can improve alignment accuracy.

(Structure of the Invention) The method for manufacturing an alignment mark of this invention includes:
A stand larger than the alignment mark is formed on the base film using an oxide film or polysilicon, and the alignment mark is formed on the center of the stand.

(Example) Hereinafter, an example of the method for manufacturing an alignment mark of the present invention will be described based on the drawings. Third
Figures a through 3f are process explanatory diagrams of one embodiment. In the case of this embodiment, as in the conventional case described in FIG. 2, an example is shown in which an alignment mark is created by a photolithography process using polysilicon used as a gate and wiring material.

First, as shown in FIG. 3a, an oxide film 32 is formed on a base film 31 such as a semiconductor silicon substrate or an oxide film.
Form with a thickness of 200 to 1000 Å. This oxide film 32
is formed using the gate insulating film material of a MOS transistor.

A polysilicon film 33 is formed on the oxide film 32 at a temperature of 2000~
Formed with a thickness of 5000 Å. The polysilicon film 33
Formed using the gate electrode material of a MOS transistor.

Next, as shown in FIG. 3b, an oxide film 32,
The oxide film 32 and polysilicon film 33 on the base film 31 are removed by a photolithography process so that a pattern in a region where the polysilicon film 33 is larger than the alignment mark remains. As a result, the polysilicon film 33 forming a pattern larger than the alignment mark becomes a base for the alignment mark.

Next, as shown in FIG. 3c, after forming an oxide film 34 with a thickness of 200 to 1000 Å, a polysilicon film 35 that also serves as an alignment mark is formed with a thickness of 2000 to 5000 Å.
Form on the entire surface.

Next, as shown in FIGS. 3d and 3e, the oxide film 34 and the polysilicon film 35 are etched to form an alignment mark region A on the polysilicon film 33 that will serve as a base for the alignment mark. do.

Area A of this alignment mark is the oxide film 34.
and a polysilicon film 35, and is formed at the center of the polysilicon film 33, which serves as a base for the alignment mark.

Next, as shown in FIG. 3f, a base film 31,
A film to be etched 3 is formed on the polysilicon films 33 and 35.
6 (PSG film, 5000 to 12000 Å) is formed, and then a resist is applied to a thickness of about 5000 to 20000 Å to form a resist film 37.

At this time, it is confirmed that the thickness of the resist film 37 on the area A of the alignment mark is thinner, for example, 10,000 to 11,000 Å, compared to the conventional thickness 26 of 12,000 to 13,000 Å shown in FIG. 1c. be done.

Therefore, when alignment is performed using the alignment mark manufactured according to the present invention, the variation in alignment accuracy is less than that of the conventional method.
In this invention, ±0.3-0.4μm compared to 0.4-0.55μm
The value of m is confirmed.

Furthermore, in terms of alignment time as well as alignment accuracy, the time it took to align 100 chips on a 4-inch wafer was 60~60~
100 seconds, whereas the alignment mark manufactured according to the present invention takes 40 to 70 seconds, confirming an improvement in throughput.

This invention is shown in FIGS. 2a to 2c and 3a to 3c.
As shown in FIG. 3f, no matter which photolithography process is used several times to create a device such as a V-LSI, it is only necessary to make a polysilicon film 33 that will serve as a base under the alignment mark. This can be achieved by simply inserting the pattern 33' of the polysilicon film 33, which will serve as a support, into the mask used in that process. Therefore, there is no need to change any conventional process.

FIGS. 4a to 4e are process explanatory diagrams of another embodiment of the present invention, and show an embodiment in which an alignment mark is manufactured on an oxide film of a LOCOS structure.

First, as shown in FIG.
A nitride film 43 is formed on it to a thickness of 2000~2000mm.
Forms about 3000Å.

Next, as shown in FIG. 4b, the oxide film 42 and nitride film 43 are etched by a photolithography process.
Expose the area where the LOCOS structure oxide film will be formed,
Using the oxide film 42 and nitride film 43 remaining on the base film 41 as a mask, as shown in FIG.
A structural oxide film 44 is formed.

The oxide film 44 of this LOCOS structure has a thickness of 6000~
The oxide film 44 of this LOCOS structure is made to have a thickness of 10,000 Å and protrudes from the upper surface of the base film 41.
is the base of the alignment mark.

Next, after forming the oxide film 44 of this LOCOS structure, the oxide film 42 and nitride film 43 on the base film 41 are removed.

Next, as shown in FIG. 4d, an oxide film 45 is formed on the base film 41 and the oxide film 44 to a thickness of 200 to 1000 Å.
A polysilicon film 46, which will become an alignment mark, is formed to a thickness of about 2000 to 5000 Å.

Next, the oxide film 45 and polysilicon film 46 are removed on the oxide film 44 of the LOCOS structure, leaving an alignment mark region A. This alignment mark region A is formed at the same time as the formation of the MOS transistor, the oxide film 45 is formed of the first or second gate insulating film, and the polysilicon film 46 serving as the alignment mark is formed of the first or second gate electrode material. It is formed.

In this way, in the present invention, by forming a stand for the alignment mark, the alignment mark can be placed with a larger step than the surface of the base film.

As a result, when a resist film is formed on the surface of the alignment mark, the thickness of the resist film on the surface of the region A of the alignment mark becomes thinner, the edges of the alignment mark become more visible, and the number of manufacturing steps is not increased. Moreover, in this invention, the table is made larger than the alignment mark and has a convex side cross section to increase the step difference, so unlike the case where the height difference of the alignment mark is simply increased and the step difference is increased, it is possible to avoid miscoverage of the resist film. This allows the resist film on the alignment mark to be made thinner.

(Effects of the Invention) As described above, according to the method for manufacturing an alignment mark of the present invention, a base larger than the alignment mark is formed on the base film using an oxide film or polysilicon, and the center base of the base is Since alignment marks are formed, miscovering of the resist film on the alignment marks can be prevented, and the thickness of the resist film only on the alignment mark areas can be reduced, improving the visibility of the alignment marks and improving alignment accuracy. This method has the advantage of not increasing the number of manufacturing steps.

[Brief explanation of the drawing]

Figure 1 shows the relationship between alignment accuracy and resist film thickness on alignment marks.
Figures a to 2c are process explanatory diagrams of a conventional alignment mark manufacturing method, respectively, and Figures 3a to 3f are process explanatory diagrams of an embodiment of the alignment mark manufacturing method of the present invention, respectively. 4a to 4e are process explanatory views of other embodiments of the alignment mark manufacturing method of the present invention, respectively. 31, 41... Base film, 32, 42, 34, 4
5...Oxide film, 33, 35, 46...Polysilicon film, 33'...Pattern to be a base, 36...
...Etched film, 37...Resist film, A...
Alignment mark area.

Claims (1)

[Claims] 1. A semiconductor device manufacturing method in which a film to be etched is formed on a base film having alignment marks on its surface, and a resist film for photolithography is applied thereon. A method for manufacturing an alignment mark, comprising the steps of: forming a pedestal made of silicon that is larger than the alignment mark; and forming an alignment mark on the center of the pedestal.