JPS6351102B2 - - Google Patents

Info

Publication number
JPS6351102B2
JPS6351102B2 JP56125729A JP12572981A JPS6351102B2 JP S6351102 B2 JPS6351102 B2 JP S6351102B2 JP 56125729 A JP56125729 A JP 56125729A JP 12572981 A JP12572981 A JP 12572981A JP S6351102 B2 JPS6351102 B2 JP S6351102B2
Authority
JP
Japan
Prior art keywords
output
counter
temperature
recording head
base material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56125729A
Other languages
Japanese (ja)
Other versions
JPS5825977A (en
Inventor
Takashi Saito
Akitsugu Yamada
Kunihiko Inoe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
NTT Inc
Original Assignee
Matsushita Electronics Corp
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Nippon Telegraph and Telephone Corp filed Critical Matsushita Electronics Corp
Priority to JP12572981A priority Critical patent/JPS5825977A/en
Publication of JPS5825977A publication Critical patent/JPS5825977A/en
Publication of JPS6351102B2 publication Critical patent/JPS6351102B2/ja
Granted legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/315—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material
    • B41J2/32—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads
    • B41J2/35—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads providing current or voltage to the thermal head
    • B41J2/355—Control circuits for heating-element selection
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/315—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material
    • B41J2/32—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads
    • B41J2/35—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads providing current or voltage to the thermal head
    • B41J2/355—Control circuits for heating-element selection
    • B41J2/36—Print density control
    • B41J2/365—Print density control by compensation for variation in temperature

Landscapes

  • Electronic Switches (AREA)

Description

【発明の詳細な説明】 本発明はフアクシミリ装置、プリンタ等に用い
られる感熱記録装置に係り、特に発熱素子への通
電時間を制御する回路を改良した感熱記録装置に
関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thermal recording device used in facsimile machines, printers, etc., and more particularly to a thermal recording device in which a circuit for controlling the time period during which electricity is applied to a heating element is improved.

一般に、感熱記録装置においては、発熱素子を
備えられる記録ヘツドの基材の温度は、発熱素子
への通電の繰り返しおよび周囲の温度の変動によ
つて変化する。そして、1回の記録における通電
素子への通電を常に一定とすると、前記記録ヘツ
ドの基材の温度変化に応じて記録濃度が変化し、
前記基材の温度が高いときには記録画像が濃くな
り、低いときには淡くなる。したがつて、記録画
像に濃度むらが生じ、鮮明な記録画像を得ること
ができなくなる。
Generally, in a thermal recording device, the temperature of the base material of a recording head equipped with a heating element changes due to repeated energization of the heating element and fluctuations in ambient temperature. If the energization to the current-carrying element during one recording is always constant, the recording density changes in accordance with the temperature change of the base material of the recording head.
When the temperature of the base material is high, the recorded image becomes dark, and when the temperature of the base material is low, it becomes light. Therefore, density unevenness occurs in the recorded image, making it impossible to obtain a clear recorded image.

このため、従来より、記録ヘツドの基材の温度
変化に応じて発熱素子への通電時間を制御してい
る。第1図はこのような発熱素子への通電時間の
制御を行なう従来の感熱記録装置を示す。1は記
録ヘツドであり、1列に配列されたm×n個の発
熱素子A1〜Anoと、これらの発熱素子A1〜Anoに
直列に接続されたダイオードD1〜Dnoと、n個の
共通側端子B1〜Bnとn個の個別側端子E1〜Eoと
を存してなる。
For this reason, conventionally, the time during which electricity is applied to the heating elements has been controlled in accordance with the temperature change of the base material of the recording head. FIG. 1 shows a conventional heat-sensitive recording device that controls the time during which electricity is applied to the heating element. Reference numeral 1 denotes a recording head, which includes m×n heating elements A 1 to A no arranged in one row, and diodes D 1 to D no connected in series to these heating elements A 1 to A no . It has n common terminals B 1 to B n and n individual terminals E 1 to E o .

前記発熱素子A1〜Anoは、n個の発熱素子を1
ブロツクとし、m個のブロツクに区分されてい
る。そして、各ブロツクの発熱体A1〜Anoの一端
は、それぞれ共通側端子B1〜Bnにまとめて接続
されている。また、各ブロツクにおいて対応する
位置にある発熱体A1〜Anoの他端は、ダイオード
D1〜Dnoを介してそれぞれ個別側端子E1〜Eoにま
とめて接続されている。
The heating elements A 1 to A no are composed of n heating elements.
The block is divided into m blocks. One ends of the heating elements A 1 to A no of each block are collectively connected to common side terminals B 1 to B n , respectively. In addition, the other end of the heating element A 1 to A no located at the corresponding position in each block is a diode.
They are collectively connected to individual side terminals E 1 to E o via D 1 to D no .

前記共通側端子B1〜Bnはそれぞれトランジス
タF1〜Fnを介して発熱素子電源端子13に接続
されている。また、個別側端子E1〜Eoは、それ
ぞれトランジスタG1〜Goを介して接地されてい
る。
The common terminals B 1 to B n are connected to the heating element power supply terminal 13 via transistors F 1 to F n , respectively. Further, the individual terminals E 1 to E o are grounded via transistors G 1 to G o , respectively.

2は記録ヘツド1の基材またはその近傍に設置
され、記録ヘツドの基材の温度変化に応じて抵抗
値を変化する温度検出素子、3は抵抗、4は温度
検出素子電源端子である。
Reference numeral 2 designates a temperature detection element which is installed on or near the base material of the recording head 1 and changes its resistance value in response to changes in the temperature of the base material of the recording head, 3 is a resistor, and 4 is a power supply terminal for the temperature detection element.

5〜8は、基準電圧源端子9と接地との間に直
列に接続された抵抗であり、互いの接続点から基
準電圧a1〜a3を取り出される。J1〜J3は比較器で
あり、それぞれ基準電圧a1〜a3と、記録ヘツド1
の温度変化に応じて変化する温度検出素子2の出
力電圧bとを比較する。
5 to 8 are resistors connected in series between the reference voltage source terminal 9 and the ground, and reference voltages a 1 to a 3 are taken out from their connection points. J 1 to J 3 are comparators, which respectively output the reference voltages a 1 to a 3 and the recording head 1.
The output voltage b of the temperature detection element 2, which changes according to the temperature change, is compared with that of the temperature detection element 2.

10は比較器J1〜J3の出力C1〜C3を2進符号に
変換するデコーダである。したがつて、このデコ
ーダ10の出力d1,d2は、段階的に記録ヘツド1
の基材の温度に対応する値となる。そして後述す
るようにこのデコーダ10出力d1,d2により発熱
素子A1〜Anoの通電時間が決定される。
10 is a decoder that converts the outputs C 1 to C 3 of the comparators J 1 to J 3 into binary codes. Therefore, the outputs d 1 , d 2 of this decoder 10 are sent to the recording head 1 in stages.
The value corresponds to the temperature of the base material. As will be described later, the energization time of the heating elements A 1 to A no is determined by the outputs d 1 and d 2 of the decoder 10.

11は走査タイミング発生回路であり、クロツ
ク入力端子1から入力するクロツクeに基づい
て、タイミングパルスf,g,hを出力する。1
4は共通側選択回路であり、そのm個の出力i1〜
inを、タイミングパルスfに同期して、順次ハイ
レベル(以下、ハイレベルを“H”ロウレベルを
“L”と略記する)とすることにより、トランジ
スタF1〜Fnを順次オンする。
Reference numeral 11 denotes a scanning timing generation circuit, which outputs timing pulses f, g, h based on the clock e inputted from the clock input terminal 1. 1
4 is a common side selection circuit, and its m outputs i 1 ~
In synchronization with the timing pulse f , the transistors F1 to Fn are sequentially turned on by sequentially setting the signal to a high level (hereinafter, high level is abbreviated as "H" and low level as "L").

15は直列入力並列出力シフトレジスタであ
り、画信号入力端子16から1ライン毎に直列入
力する画信号jを並列出力する。17はパルス発
生回路であり、クロツクe,タイミングパルスh
およびデコーダ10の出力d1,d2に基づいて、ト
ランジスタF1〜Fnがそれぞれオンされている期
間毎にパルス幅tの通電時間制御パルスkを出力
する。ここで、前記パルス幅tは、デコーダ10
の出力d1,d2によつて決定される。
Reference numeral 15 denotes a serial input/parallel output shift register, which outputs in parallel the image signal j that is input in series from the image signal input terminal 16 for each line. 17 is a pulse generation circuit, which generates a clock e and a timing pulse h.
Based on the outputs d 1 and d 2 of the decoder 10, an energization time control pulse k having a pulse width t is output for each period in which each of the transistors F 1 to F n is turned on. Here, the pulse width t is the decoder 10
is determined by the outputs d 1 and d 2 of .

K1〜Koは、それぞれシフトレジスタ15の並
列出力11〜1oを一方の入力とし、通電時間制御
パルスkを共通に他方の入力とする2入力AND
ゲートであり、これらのANDゲートK1〜Koの出
力によりトランジスタG1〜Goがそれぞれオン、
オフされる。
K 1 to K o are two-input ANDs in which the parallel outputs 1 1 to 1 o of the shift register 15 are used as one input, and the energization time control pulse k is commonly used as the other input.
The outputs of these AND gates K 1 to K o turn on transistors G 1 to G o , respectively.
It will be turned off.

さて、シフトレジスタ15の出力11〜1oのう
ちの黒信号のビツトに対応するものは“H”とな
る。したがつて、通電時間制御パルスkがパルス
発生回路17から出力されると、黒信号のビツト
に対応するANDゲートK1〜Koのアンド条件が成
立し、これに対応するトランジスタG1〜Goがオ
ンされる。
Of the outputs 1 1 to 1 o of the shift register 15, those corresponding to the black signal bits become "H". Therefore, when the energization time control pulse k is output from the pulse generation circuit 17, the AND condition of the AND gates K 1 to K o corresponding to the bits of the black signal is established, and the corresponding transistors G 1 to G o is turned on.

そして、通電時間制御パルスkは、前記のよう
に各トランジスタF1〜Fnが順次オンされている
期間毎に出力されるので、結局、各ブロツク毎
に、発熱素子電源端子13から黒信号のビツトに
対応する発熱素子A1〜Anoに一括して通電が行わ
れることになる。
Since the energization time control pulse k is output for each period in which each of the transistors F 1 to F n is sequentially turned on as described above, the black signal is output from the heating element power supply terminal 13 for each block. The heating elements A 1 to A no corresponding to the bits are energized all at once.

ここにおいて、各発熱素子A1〜Anoへの通電時
間は、アンドゲートK1〜Koが開いている時間、
すなわち、通電時間制御パルスkとパルス幅tに
対応する。そして、このパルス幅はデコーダ10
の出力d1,d2、ひいては記録ヘツド1の基材の温
度に対応するので、結局、前記通電時間は記録ヘ
ツド1の基材の温度に応じて段階的に変化される
ことになる。しかし、この従来装置では前記通電
時間の長さの段階を多数とするには、a1〜a3に相
当する基準電圧の数、ひいてはJ1〜J3に相当する
比較器の数を増加しなければならぬが、前記比較
器を多数とすることは、コストおよび実装面積等
の制約から困難であるので、前記比較器の数は
2,3に留めざるをえなかつた。
Here, the energization time to each heating element A 1 to A no is the time during which the AND gates K 1 to K o are open;
That is, it corresponds to the energization time control pulse k and the pulse width t. This pulse width is determined by the decoder 10
The outputs d 1 and d 2 of the recording head 1 correspond to the temperature of the base material of the recording head 1, so that the current application time is changed in stages according to the temperature of the base material of the recording head 1. However, in this conventional device, in order to increase the number of stages of the length of the energization time, the number of reference voltages corresponding to a 1 to a 3 and, by extension, the number of comparators corresponding to J 1 to J 3 must be increased. However, it is difficult to increase the number of comparators due to constraints such as cost and mounting area, so the number of comparators has to be limited to two or three.

したがつて、発熱素子への通電時間の制御が十
分な精度で行われず、記録ヘツド1の基材の温度
上昇とともに得られる記録画像に明らかな濃淡変
化が認められるようになり、例えば一通の前半は
濃く、後半は淡いということも生じ、所期の効果
を十分得られないという欠点があつた。
Therefore, the time during which electricity is applied to the heating element is not controlled with sufficient precision, and as the temperature of the base material of the recording head 1 increases, obvious changes in density are observed in the recorded image. There were cases where the first half was dark and the second half was pale, which had the disadvantage that the desired effect could not be obtained sufficiently.

本発明は、前記従来の欠点を解消するべくなさ
れたもので、実装、コスト等の面で不都合を生じ
ることなく、記録ヘツドの基材の温度変化に応じ
て発熱素子への通電時間を細かく切り換え、記録
ヘツド温度制御を精度良く行い、常に一定濃度の
美しい記録画像を得ることができる感熱記録装置
を提供することを目的とする。
The present invention has been made in order to eliminate the above-mentioned conventional drawbacks, and is capable of finely switching the energization time to the heating element according to the temperature change of the base material of the recording head without causing any inconvenience in terms of implementation, cost, etc. An object of the present invention is to provide a heat-sensitive recording device that can accurately control the temperature of a recording head and always obtain beautiful recorded images with a constant density.

以下本発明を図面に示す実施例に基づいて説明
する。第2および第3図は本発明の一実施例を示
す。2は前記従来装置の場合と同様の温度検出素
子であり、この温度検出素子の一端は接地され、
他端は抵抗3を介して温度検出素子電源端子4に
接続されている。18は比較器であり、温度検出
素子2と抵抗3との接続点から出力される温度検
出素子2の出力電圧bとD/A変換器19の出力
Pとを比較し、bがpより高いときにその出力q
を“H”とする。
The present invention will be described below based on embodiments shown in the drawings. Figures 2 and 3 illustrate one embodiment of the invention. 2 is a temperature detection element similar to that of the conventional device, one end of which is grounded;
The other end is connected to a temperature detection element power supply terminal 4 via a resistor 3. 18 is a comparator, which compares the output voltage b of the temperature detection element 2 outputted from the connection point between the temperature detection element 2 and the resistor 3 and the output P of the D/A converter 19, and determines that b is higher than p. When its output q
is set to “H”.

30は比較器18の出力qと、通電時間制御用
クロツク入力端子20から入力する通電時間制御
用クロツクrとを入力するANDゲートである。
なお、このANDゲート30の入力として、本回
路を動作可能な状態にするイネーブル信号Sを追
加してもよい(この場合イネーブル信号Sが
“H”となると、本回路は動作可能な状態とな
る)。21は、ANDゲート30の出力y、すなち
ANDゲート30を通して入力するクロツクrを
カウントする3段のバイナリーカウンタであり、
リセツト信号入力端子22からリセツト信号uを
入力すると、クリアー状態となる。前記D/A変
換器19はカウンタ21の各段の出力x1〜x3を
D/A変換するものである。
30 is an AND gate which receives the output q of the comparator 18 and the energization time control clock r inputted from the energization time control clock input terminal 20.
Note that an enable signal S that makes the circuit ready for operation may be added as an input to the AND gate 30 (in this case, when the enable signal S becomes "H", the circuit becomes ready for operation). ). 21 is the output y of the AND gate 30, i.e.
It is a three-stage binary counter that counts the clock r input through the AND gate 30.
When the reset signal u is inputted from the reset signal input terminal 22, it becomes a clear state. The D/A converter 19 converts the outputs x 1 to x 3 of each stage of the counter 21 into a D/A converter.

17は前記従来装置の場合と同様のパルス発生
回路であり、第3図はこのパルス発生回路17の
具体的構成例を示す。すなわち、第3図におい
て、パルス発生回路17はROM23、カウンタ
24、インバータ25およびANDゲート26か
らなる。前記ROM23は、カウンタ21の出力
x1〜x3をアドレス入力として、あらかじめ書き込
まれている通電時間設定データを読み出される。
Reference numeral 17 denotes a pulse generating circuit similar to that of the conventional device, and FIG. 3 shows a specific example of the configuration of this pulse generating circuit 17. That is, in FIG. 3, the pulse generating circuit 17 includes a ROM 23, a counter 24, an inverter 25, and an AND gate 26. The ROM 23 stores the output of the counter 21.
By using x 1 to x 3 as address inputs, pre-written energization time setting data is read out.

前記ANDゲート26は、一方の入力に前記従
来装置と同様の走査タイミング発生回路(図示せ
ず)からクロツクeを入力し、他方の入力にカウ
ンタ24のキヤリー出力zをインバータ25を介
して入力する。また、前記カウンタ24は、クロ
ツク入力にANDゲート26を介してクロツクe
を入力し、ロード入力に前記走査タイミング発生
回路からタイミングパルスhを入力する。そし
て、同カウンタ24は、タイミングパルスhを入
力すると、ROM23の出力をプリセツト値とし
てロードされる。通電時間制御パルスkは、イン
バータ25から出力される。
The AND gate 26 receives a clock e from a scan timing generation circuit (not shown) similar to the conventional device at one input, and receives the carry output z of the counter 24 via an inverter 25 at the other input. . The counter 24 also receives a clock e via an AND gate 26 at its clock input.
is input, and the timing pulse h from the scan timing generation circuit is input to the load input. When the counter 24 receives the timing pulse h, the output of the ROM 23 is loaded as a preset value. The energization time control pulse k is output from the inverter 25.

次に、本実施例の動作を第4図および第5図に
示すタイムチヤートおよび電圧波形図とともに説
明する。なお、第4図のタイムチヤートは、数十
分間の時間の経過を示しているが、同図中のt1,
t2のみは便宜上非常に大きく拡大して描いてい
る。
Next, the operation of this embodiment will be explained with reference to time charts and voltage waveform diagrams shown in FIGS. 4 and 5. Note that the time chart in Figure 4 shows the passage of time over several tens of minutes, but t 1 ,
Only t 2 is enlarged and drawn for convenience.

まず記録ヘツド1の基材の温度がほぼ室温に近
い状態になつている時に、本装置の動作が開始さ
れたとすると、この動作開始時には温度検出素子
2の出力電圧bは第4図のbの曲線の左端の点W
で示されるように低い値となつている。
First, if the operation of this apparatus is started when the temperature of the base material of the recording head 1 is close to room temperature, then at the start of this operation, the output voltage b of the temperature detection element 2 is as shown in b of FIG. Point W at the left end of the curve
As shown, the value is low.

そして、この動作開始時にカウンタ21にリセ
ツト信号uが与えられると、同カウンタ21の出
力x1〜x3は“0”となり、D/A変換器19の出
力Pはその最低電圧となる。ここで、このD/A
変換器19の最低電圧は、記録ヘツド1の基材の
温度が室温付近にある場合の温度検出素子2の出
力電圧bより低く設定されている。したがつて、
比較器18の出力qは“H”となる。
When the reset signal u is applied to the counter 21 at the start of this operation, the outputs x1 to x3 of the counter 21 become "0" and the output P of the D/A converter 19 becomes its lowest voltage. Here, this D/A
The lowest voltage of the converter 19 is set lower than the output voltage b of the temperature detection element 2 when the temperature of the substrate of the recording head 1 is around room temperature. Therefore,
The output q of the comparator 18 becomes "H".

これにより、ANDゲート30が開かれ、クロ
ツクrがカウンタ21へ入力され、カウンタ21
が同クロツクrを計数するので、カウンタ21の
出力x1〜x3は(000)→(001)→(010)→…と
変化する。すると、これに伴つてD/A変換器1
9の出力Pが階段状に上昇して行く。
As a result, the AND gate 30 is opened, the clock r is input to the counter 21, and the clock r is input to the counter 21.
counts the same clock r, so the outputs x 1 to x 3 of the counter 21 change as (000) → (001) → (010) → . Then, along with this, the D/A converter 1
9's output P rises in a stepwise manner.

このような動作が続けられると、いずれD/A
変換器19の出力Pの方が温度検出素子2の出力
bよりレベルが高くなり、そのとき比較器18の
出力qは“L”となり、ANDゲート30は閉じ
られる。
If this kind of operation continues, the D/A
The output P of the converter 19 has a higher level than the output b of the temperature detection element 2, and at this time the output q of the comparator 18 becomes "L" and the AND gate 30 is closed.

したがつて、クロツクrがカウンタ21に入力
されなくなり、同カウンタ21の出力x1〜x3は変
化しなくなるので、第4図イの部分で示されるよ
うにD/A変換器19の出力Pは一定値に保持さ
れるようになる。
Therefore, the clock r is no longer input to the counter 21, and the outputs x1 to x3 of the counter 21 do not change, so that the output P of the D/A converter 19 as shown in part A of FIG. will be held at a constant value.

しかし、後で詳しく説明するように、前記動作
開始以後、カウンタ21の出力x1〜x3に対応する
通電時間にて発熱素子への通電が繰り返されてい
るので、さらに時間が経過すると、記録ヘツド1
の基材の温度が上昇してきて、温度検出素子2の
出力bの方がD/A変換器19の出力Pより高い
レベルになる。これにより比較器18の出力qが
再び“H”となり、ANDゲート30が開き、カ
ウンタ21はクロツクrを1つ計数する。
However, as will be explained in detail later, after the start of the operation, the heating element is repeatedly energized for the energization time corresponding to the outputs x 1 to x 3 of the counter 21, so that if further time elapses, the recording Head 1
The temperature of the base material increases, and the output b of the temperature detection element 2 becomes higher than the output P of the D/A converter 19. As a result, the output q of the comparator 18 becomes "H" again, the AND gate 30 opens, and the counter 21 counts one clock r.

すると、同カウンタ21の出力x1〜x3の値は1
だけ増加し、D/A変換器19の出力bもそれに
見合うだけ上昇するので、ロのようにPの方がb
よりまたレベルが高くなる。
Then, the value of the output x 1 to x 3 of the counter 21 is 1
, and the output b of the D/A converter 19 also increases accordingly, so as shown in b, P is higher than b.
The level will be higher again.

したがつて、比較器18の出力qは“L”とな
り、ANDゲート30が閉じられ、カウンタ21
はクロツクrを計数しなくなる。
Therefore, the output q of the comparator 18 becomes "L", the AND gate 30 is closed, and the counter 21
will no longer count the clock r.

そして、以後同様の動作が繰り返され、A/D
変換器19の出力Pは常に温度検出素子2の出力
bよりやや高い点で安定しようとするので、D/
A変換器19の出力Pは記録ヘツド1の基材の温
度にほぼ対応した値となる。
Then, the same operation is repeated thereafter, and the A/D
Since the output P of the converter 19 always tries to stabilize at a point slightly higher than the output b of the temperature detection element 2, D/
The output P of the A converter 19 has a value approximately corresponding to the temperature of the base material of the recording head 1.

これゆえ、次のようにしてカウンタ21の出力
x1〜x3に応じて発熱素子への通電時間が制御され
ることにより、記録ヘツド1の基材の温度に応じ
て前記通電時間が制御されることになる。
Therefore, the output of the counter 21 is as follows.
By controlling the energizing time to the heating elements according to x 1 to x 3 , the energizing time can be controlled depending on the temperature of the base material of the recording head 1 .

すなわち、カウンタ21の出力x1〜x3がアドレ
ス入力となることにより、このx1〜x3に対応する
値の通電時間設定データがROM23から読み出
される。そして、この通電時間設定データがタイ
ミングパルスhをタイミングとしてカウンタ24
にプリセツト値としてロードされる。すると、カ
ウンタ24のキヤリー出力zが“L”となり、
ANDゲート26が開かれ、カウンタ24は同ゲ
ート26を通して入力するクロツクeを計数し始
める。そして、カウンタ25が前記プリセツト値
によつて決定される数だけクロツクeを計数する
と、同カウンタ24のキヤリー出力zは“H”と
なる。
That is, the outputs x 1 to x 3 of the counter 21 serve as address inputs, so that the energization time setting data of the values corresponding to these x 1 to x 3 are read from the ROM 23 . Then, this energization time setting data is applied to the counter 24 using the timing pulse h as the timing.
loaded as a preset value. Then, the carry output z of the counter 24 becomes "L",
The AND gate 26 is opened, and the counter 24 starts counting the clock e input through the AND gate 26. When the counter 25 counts the number of clocks e determined by the preset value, the carry output z of the counter 24 becomes "H".

すると、ゲート26が閉じられるので、カウン
タ24はクロツクeを入力されなくなるため、前
記キヤリー出力zはそのまま“H”に保持され
る。
Then, since the gate 26 is closed, the clock e is no longer input to the counter 24, so the carry output z is maintained at "H".

そして、次のタイミングパルスhがカウンタ2
4のロード入力に入力され、ROM23から新た
な通電時間設定データがプリセツト値としてカウ
ンタ24にロードされると、キヤリー出力zが再
び“L”となり、前記同様の動作が繰り返され
る。したがつて、キヤリー出力zの反転信号であ
る通電時間制御パルスkは、前記通電時間設定デ
ータ、ひいてはカウンタ21の出力x1〜x3に対応
する時間だけ“H”になることになる。これによ
り、前記のように記録ヘツド1の基材の温度に応
じて発熱素子へ通電時間が制御される。
Then, the next timing pulse h is detected by counter 2.
When the new energization time setting data is inputted to the load input of No. 4 and loaded from the ROM 23 into the counter 24 as a preset value, the carry output z becomes "L" again, and the same operation as described above is repeated. Therefore, the energization time control pulse k, which is an inverted signal of the carry output z, becomes "H" only for the time corresponding to the energization time setting data, and thus the outputs x1 to x3 of the counter 21. As a result, the time for energizing the heating element is controlled in accordance with the temperature of the base material of the recording head 1, as described above.

前記通電時間制御パルスkのパルス幅tは、記
録ヘツド1の基材の温度が高くなるにつれて短く
なるようにしなければならないが、その具体的な
値は、記録ヘツド1の特性、記録紙の特性、およ
び記録速度等に応じて設定する必要がある。第5
図は、カウンタ21の出力x1〜x3がとる各値に対
する通電時間制御信号kのパルス幅tの設定例を
示す。
The pulse width t of the energization time control pulse k must be made shorter as the temperature of the base material of the recording head 1 increases, but its specific value depends on the characteristics of the recording head 1 and the characteristics of the recording paper. , recording speed, etc. Fifth
The figure shows an example of setting the pulse width t of the energization time control signal k for each value taken by the outputs x 1 to x 3 of the counter 21.

なお、第5図において、x1〜x3が“7”の場合
のkのパルス幅tが非常に狭くなつているが、こ
れは万一何らかの原因により記録ヘツド1の基材
が異常に高温になつた場合には、発熱素子へ印加
する電力を非常に小さくして、記録ヘツドO破壊
を防止するためである。
In addition, in FIG. 5, the pulse width t of k when x 1 to x 3 is "7" is very narrow, but this is due to the fact that the base material of the recording head 1 is at an abnormally high temperature due to some reason. This is to prevent damage to the recording head O by reducing the power applied to the heating element to a very low level when the temperature decreases.

ところで、カウンタ21の出力x1〜x3は、記録
ヘツド1の基材の温度が上昇している時には、前
記のように温度検出素子2の出力bに追従して行
くが、記録ヘツド1の基材の温度が降下する場合
には、追従しない。したがつて第4図のタイムチ
ヤートの右端付近に示すように適当なタイミング
においてリセツトパルスuをカウンタ21に与
え、同カウンタ21をリセツトする必要がある。
そして、このリセツトの後は、カウンタ21の出
力x1〜x3は再び温度検出素子2の出力bに追従し
ていく。
Incidentally, when the temperature of the base material of the recording head 1 is rising, the outputs x 1 to x 3 of the counter 21 follow the output b of the temperature detection element 2 as described above, but the outputs x 1 to x 3 of the recording head 1 follow If the temperature of the base material decreases, it will not follow. Therefore, it is necessary to reset the counter 21 by applying a reset pulse u to the counter 21 at an appropriate timing as shown near the right end of the time chart in FIG.
After this reset, the outputs x 1 to x 3 of the counter 21 follow the output b of the temperature detection element 2 again.

ここで、リセツトパルスuが出力されてから
D/A変換器19の出力Pが温度検出素子2の出
力bとほぼ等しくなるまでにかかる時間(第5図
におけるt1,t2に相当する時間)は、クロツクr
の周波数に依存し、同周波数が高いほどその時間
は短くなる。そして、クロツクrはいくら高くし
ても(数Mzまで)他に悪影響が出ないので、前
記時間は他の動作タイミングに比べ十分無視でき
るほど短くできるため(前記のように第5図の
t1,t2は便宜上拡大して描いてある)、リセツト
信号uの出力を各ラインの走査の合間毎に行い記
録画像に影響が生じないようにすることができ
る。
Here, the time required for the output P of the D/A converter 19 to become almost equal to the output b of the temperature detection element 2 after the reset pulse u is output (the time corresponding to t 1 and t 2 in FIG. ) is clock r
The higher the frequency, the shorter the time. Furthermore, no matter how high the clock r is (up to a few Mz), there is no adverse effect on other operations, so the above-mentioned time can be shortened to the point where it can be ignored compared to other operation timings (as mentioned above, as shown in Figure 5).
t 1 and t 2 are shown enlarged for convenience), the reset signal u can be outputted every interval between scanning of each line so as not to affect the recorded image.

さて、本装置では、カウンタ21の出力および
パルス発生回路17の入力のビツト数を増加する
だけで、発熱素子への通電時間の調整段階数を増
加できるので、前記従来装置のように部品点数の
増加による実装上の問題やコスト上昇を招くこと
なく記録ヘツド1の基材の温度変化に応じて発熱
素子への通電時間を非常に細く調整することがで
きる。
Now, in this device, the number of adjustment steps for the energization time to the heat generating element can be increased simply by increasing the number of bits of the output of the counter 21 and the input of the pulse generation circuit 17. It is possible to adjust the energization time to the heat generating elements very narrowly according to the temperature change of the base material of the recording head 1 without causing mounting problems or cost increases due to the increase.

そして、これにより常に一定な濃度の美しい記
録画像を得ることができるとともに、記録ヘツド
1の温度が異常に上昇する虞れも非常に少なくな
る。
As a result, it is possible to always obtain a beautiful recorded image with a constant density, and the possibility that the temperature of the recording head 1 rises abnormally is greatly reduced.

以上のように本発明による感熱記録装置は、記
録ヘツドの基材の温度を検出する温度検出素子
と、カウンタと、このカウンタの出力をD/A変
換するD/A変換器と、このD/A変換器の出力
と、前記温度検出素子の出力とを比較する比較器
と、前記カウンタの出力に応じて前記発熱素子へ
の通電時間を制御する回路とを有してなり、前記
カウンタは前記比較器の出力に応じてクロツクの
計数を行うようにしたことにより、実装上の問題
やコスト上昇を招くことなく、記録ヘツドの基材
の温度変化に応じて発熱素子への通電時間を細か
く制御し、記録濃度を常に一定にすることができ
るという優れた効果を得られるものである。
As described above, the thermal recording device according to the present invention includes a temperature detection element that detects the temperature of the base material of the recording head, a counter, a D/A converter that converts the output of the counter into D/A, and the D/A converter that converts the output of the counter into D/A. It has a comparator that compares the output of the A converter and the output of the temperature detection element, and a circuit that controls the energization time to the heating element according to the output of the counter, and the counter By counting the clocks according to the output of the comparator, it is possible to precisely control the energization time to the heating element according to the temperature change of the recording head base material, without causing mounting problems or increasing costs. However, an excellent effect can be obtained in that the recording density can always be kept constant.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の感熱記録装置を示す回路図、第
2図は本発明による感熱記録装置の一実施例の要
部を示す回路図、第3図は前記実施例におけるパ
ルス発生回路の具体的構成例を示す回路図、第4
図は前記実施例のタイミングチヤート、第5図は
前記実施例における通電時間制御パルスのパルス
幅の設定例を示す電圧波形図である。 1……記録ヘツド、2……温度検出素子、17
……パルス発生回路、18……比較器、19……
D/A変換器、21……カウンタ、30……
ANDゲート、A1〜Ano……発熱素子、r……通
電時間制御用クロツク。
FIG. 1 is a circuit diagram showing a conventional thermal recording device, FIG. 2 is a circuit diagram showing main parts of an embodiment of the thermal recording device according to the present invention, and FIG. 3 is a specific diagram of a pulse generating circuit in the embodiment. Circuit diagram showing a configuration example, No. 4
The figure is a timing chart of the embodiment, and FIG. 5 is a voltage waveform diagram showing an example of setting the pulse width of the energization time control pulse in the embodiment. 1... Recording head, 2... Temperature detection element, 17
...Pulse generation circuit, 18...Comparator, 19...
D/A converter, 21... Counter, 30...
AND gate, A 1 ~ A no ...Heating element, r...Clock for controlling energization time.

Claims (1)

【特許請求の範囲】[Claims] 1 発熱素子を備えた記録ヘツドと、この記録ヘ
ツドの基材の温度を検出する温度検出素子と、ク
ロツクを計数する計数手段と、この計数手段の出
力をD/A変換するD/A変換手段と、このD/
A変換手段の出力と前記温度検出素子の出力とを
比較する比較手段と、前記計数手段の出力に応じ
て前記発熱素子への通電時間を段階的に制御する
手段とを有してなり、前記比較手段の前記温度検
出素子の出力と前記D/A変換手段の出力との不
一致検知信号により前記計数手段がクロツクの計
数を行うよう構成された感熱記録装置。
1. A recording head equipped with a heating element, a temperature detection element for detecting the temperature of the base material of the recording head, a counting means for counting clocks, and a D/A conversion means for converting the output of the counting means from D/A. And this D/
Comparing means for comparing the output of the A converting means and the output of the temperature detecting element, and means for controlling the energization time to the heating element in stages according to the output of the counting means, A thermosensitive recording device, wherein the counting means counts clocks based on a discrepancy detection signal between the output of the temperature detecting element of the comparing means and the output of the D/A converting means.
JP12572981A 1981-08-11 1981-08-11 Thermal recorder Granted JPS5825977A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12572981A JPS5825977A (en) 1981-08-11 1981-08-11 Thermal recorder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12572981A JPS5825977A (en) 1981-08-11 1981-08-11 Thermal recorder

Publications (2)

Publication Number Publication Date
JPS5825977A JPS5825977A (en) 1983-02-16
JPS6351102B2 true JPS6351102B2 (en) 1988-10-12

Family

ID=14917332

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12572981A Granted JPS5825977A (en) 1981-08-11 1981-08-11 Thermal recorder

Country Status (1)

Country Link
JP (1) JPS5825977A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05304592A (en) * 1992-11-02 1993-11-16 Matsushita Graphic Commun Syst Inc Thermosensing recorder
US20020084928A1 (en) * 2000-12-29 2002-07-04 Nale William H. Method and apparatus for time multiplexing of thermal sensor

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6128516A (en) * 1984-07-20 1986-02-08 Mitsui Petrochem Ind Ltd Low-softening point hydrocarbon polymer and its use

Also Published As

Publication number Publication date
JPS5825977A (en) 1983-02-16

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